Datasheet

AD7476A/AD7477A/AD7478A
Rev. F | Page 21 of 28
SERIAL INTERFACE
Figure 24, Figure 25, and Figure 26 show the detailed timing
diagrams for serial interfacing to the AD7476A, AD7477A, and
AD7478A, respectively. The serial clock provides the conversion
clock and also controls the transfer of information from the
AD7476A/AD7477A/AD7478A during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 24 at Point B. On the 16th SCLK falling edge,
the SDATA line goes back into three-state. If the rising edge of
CS
occurs before 16 SCLKs have elapsed, the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 24. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476A.
For the AD7477A, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next rising edge as shown
at Point B in Figure 25. If the rising edge of
CS
occurs before
14 SCLKs have elapsed, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, SDATA returns to three-state on the
16th SCLK falling edge, as shown in Figure 25.
For the AD7478A, the conversion requires 12 SCLK cycles to
complete. The track-and-hold goes back into track on the rising
edge after the 11th falling edge, as shown in Figure 26 at Point B. If
the rising edge of
CS
occurs before 12 SCLKs have elapsed, the
conversion is terminated and the SDATA line goes back into three-
state. If 16 SCLKs are considered in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 26.
CS
SCLK
S
DATA
t
2
t
6
t
3
t
4
t
7
t
5
t
8
t
CONVERT
t
QUIET
ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0
B
THREE-STATETHREE-
STATE
Z
4 LEADING ZEROS
1 3 13 14 15 16
t
1
1/THROUGHPUT
245
02930-024
Figure 24. AD7476A Serial Interface Timing Diagram
SCLK
1 5 13 15
THREE-STATE
t
4
2 16
t
5
t
3
t
2
DB9 DB8
DB0 ZERO
t
6
t
7
t
8
14
4 LEADING ZEROS
ZERO ZERO ZERO Z
t
1
1/THROUGHPUT
ZERO
2 TRAILING ZEROS
SDATA
t
CONVERT
t
QUIET
B
THREE-STATE
CS
4
02930-025
3
Figure 25. AD7477A Serial Interface Timing Diagram
CS
SCLK
1
13
15
SDATA
4 LEADING ZEROS
THREE-STATE
t
4
2
3
16
t
5
t
3
t
2
THREE-STATE
DB7
t
6
t
7
t
8
14
ZERO ZERO ZERO Z
t
1
1/ THROUGHPUT
ZERO ZERO ZERO ZERO
11 12
4 TRAILING ZEROS
t
CONVERT
t
QUIET
B
4
02930-026
Figure 26. AD7478A Serial Interface Timing Diagram