Datasheet

REV. B
–5–
AD7470/AD7472
Limit at T
MIN
, T
MAX
Parameter AD7470 AD7472 Unit Description
f
CLK
2
10 10 kHz min
30 26 MHz max
t
CONVERT
436.42 531.66 ns min t
CLK
= 1/f
CLK IN
t
WAKEUP
11µs max Wake-Up Time
t
1
10 10 ns min CONVST Pulse Width
t
2
CONVST to BUSY Delay,
10 10 ns max V
DD
= 5 V, A and B Versions
15 ns max V
DD
= 5 V, Y Version
30 30 ns max V
DD
= 3 V, A and B Versions
35 ns max V
DD
= 3 V, Y Version
t
3
00ns max BUSY to CS Setup Time
t
4
3
00ns max CS to RD Setup Time
t
5
20 20 ns min RD Pulse Width
t
6
3
15 15 ns min Data Access Time After Falling Edge of RD
t
7
4
88ns max Bus Relinquish Time After Rising Edge of RD
t
8
00ns max CS to RD Hold Time
t
9
Acquisition Time
135 135 ns max A and B Versions
140 ns max Y Version
t
10
100 100 ns min Quiet Time
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Figure 1.
2
Mark/Space ratio for the CLK inputs is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST .
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(V
DD
= 2.7 V to 5.25 V, REF IN = 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
200␮A
I
OL
200␮A
I
OH
C
L
50pF
TO OUTPUT
PIN
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications