Datasheet

AD7466/AD7467/AD7468
Rev. C | Page 9 of 28
TIMING SPECIFICATIONS
For all devices, V
DD
= 1.6 V to 3.6 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.4 V.
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.
10 kHz min 1.6 V ≤ V
DD
≤ 3 V; minimum f
SCLK
at which specifications are guaranteed.
20 kHz min V
DD
= 3.3 V; minimum f
SCLK
at which specifications are guaranteed.
150 kHz min V
DD
= 3.6 V; minimum f
SCLK
at which specifications are guaranteed.
t
CONVERT
16 × t
SCLK
AD7466.
12 × t
SCLK
AD7467.
10 × t
SCLK
AD7468.
Acquisition Time
Acquisition time/power-up time from power-down. See the
Terminology section.
The acquisition time is the time required for the part to acquire a full-scale step
input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.
780 ns max V
DD
= 1.6 V.
640 ns max 1.8 V ≤ V
DD
≤ 3.6 V.
t
QUIET
10 ns min
Minimum quiet time required between bus relinquish and the start of the next
conversion.
t
1
10 ns min
Minimum
CS pulse width.
t
2
55 ns min
CS to SCLK setup time. If V
DD
= 1.6 V and f
SCLK
= 3.4 MHz, t
2
has to be 192 ns
minimum in order to meet the maximum figure for the acquisition time.
t
3
55 ns max
Delay from
CS until SDATA is three-state disabled. Measured with the load circuit
in Figure 2 and defined as the time required for the output to cross the V
IH
or V
IL
voltage.
t
4
140 ns max
Data access time after SCLK falling edge. Measured with the load circuit in
Figure 2
and defined as the time required for the output to cross the V
IH
or V
IL
voltage.
t
5
0.4 t
SCLK
ns min SCLK low pulse width.
t
6
0.4 t
SCLK
ns min SCLK high pulse width.
t
7
10 ns min
SCLK to data valid hold time. Measured with the load circuit in
Figure 2 and
defined as the time required for the output to cross the V
IH
or V
IL
voltage.
t
8
60 ns max
SCLK falling edge to SDATA three-state. t
8
is derived from the measured time taken
by the data outputs to change 0.5 V when loaded with the circuit in
Figure 2. The
measured number is then extrapolated back to remove the effects of charging or
discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing
characteristics, is the true bus relinquish time of the part, and is independent of
the bus loading.
7 ns min SCLK falling edge to SDATA three-state.
200μAI
OL
200μAI
OH
1.4V
TO OUTPUT
PIN
C
L
50pF
02643-002
Figure 2. Load Circuit for Digital Output Timing Specifications