Datasheet

AD7466/AD7467/AD7468
Rev. C | Page 4 of 28
Parameter B Version Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
− 0.2 V min I
SOURCE
= 200 μA, V
DD
= 1.6 V to 3.6 V
Output Low Voltage, V
OL
0.2 V max I
SINK
= 200 μA
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance 10 pF max
Output Coding
Straight (natural)
binary
CONVERSION RATE
Conversion Time 4.70 μs max 16 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate 200 kSPS max See the Serial Interface section
POWER REQUIREMENTS
V
DD
1.6/3.6 V min/max
I
DD
Digital inputs = 0 V or V
DD
Normal Mode (Operational) 300 μA max V
DD
= 3 V, f
SAMPLE
= 100 kSPS
110 μA typ V
DD
= 3 V, f
SAMPLE
= 50 kSPS
20 μA typ V
DD
= 3 V, f
SAMPLE
= 10 kSPS
240 μA max V
DD
= 2.5 V, f
SAMPLE
= 100 kSPS
80 μA typ V
DD
= 2.5 V, f
SAMPLE
= 50 kSPS
16 μA typ V
DD
= 2.5 V, f
SAMPLE
= 10 kSPS
165 μA max V
DD
= 1.8 V, f
SAMPLE
= 100 kSPS
50 μA typ V
DD
= 1.8 V, f
SAMPLE
= 50 kSPS
10 μA typ V
DD
= 1.8 V, f
SAMPLE
= 10 kSPS
Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section
Normal Mode (Operational) 0.9 mW max V
DD
= 3 V, f
SAMPLE
= 100 kSPS
0.6 mW max V
DD
= 2.5 V, f
SAMPLE
= 100 kSPS
0.3 mW max V
DD
= 1.8 V, f
SAMPLE
= 100 kSPS
Power-Down Mode 0.3 μW max V
DD
= 3 V