Datasheet

AD7466/AD7467/AD7468
Rev. C | Page 23 of 28
t
1
SCLK
S
DAT
A
B
1 2 3 4 11 12
t
2
t
6
t
CONVERT
t
QUIET
4 LEADING ZEROS
THREE-STATE
THREE-STATE
8 BITS OF DATA
DB7 DB0
t
3
t
4
t
7
t
5
t
8
CS
02643-032
0
0
00
Figure 31. AD7468 Serial Interface Timing Diagram
MICROPROCESSOR INTERFACING
The serial interface on the AD7466/AD7467/AD7468 allows
the parts to be connected directly to many different micro-
processors. This section explains how to interface the AD7466/
AD7467/AD7468 with some of the more common microcontroller
and DSP serial interface protocols.
AD7466/AD7467/AD7468 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7466/AD7467/AD7468. The
CS
input allows easy inter-
facing between the TMS320C541 and the AD74xx devices,
without requiring any glue logic. The serial port of the
TMS320C541 is set up to operate in burst mode (FSM = 1
in the serial port control register, SPC) with internal CLKX
(MCM = 1 in the SPC register) and internal frame signal
(TXM = 1 in the SPC register), so both pins are configured as
outputs. For the AD7466, the word length should be set to
16 bits (FO = 0 in the SPC register). The standard synchronous
serial port interface in this DSP allows only frames with a word
length of 16 bits or 8 bits. Therefore, for the AD7467 and
AD7468 where 14 and 12 bits are required, the FO bit also
would be set up to 16 bits. In these cases, the user should keep
in mind that the last 2 bits and 4 bits for the AD7467 and
AD7468, respectively, are invalid data as the SDATA line goes
back into three-state on the 14th and 12th SCLK falling edge.
To summarize, the values in the SPC register are FO = 0,
FSM = 1, MCM = 1, and TXM = 1.
Figure 32 shows the connection diagram. For signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C541 provide equidistant sampling.
AD7466/
AD7467/
AD7468
1
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SDATA
TMS320C541
1
CLKX
CLKR
DR
FSX
FSR
02643-033
CS
Figure 32. Interfacing to the TMS320C541
AD7466/AD7467/AD7468 to ADSP-218x Interface
The ADSP-218x family of DSPs is interfaced directly to the
AD7466/AD7467/AD7468 without any glue logic. The SPORT
control register must be set up as described in
Table 9.
Table 9. SPORT Control Register Setup
Setting Description
TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right-justify data
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0 Sets up RFS as an input
ITFS = 1 Sets up TFS as an output
SLEN = 1111 16 bits for the AD7466
SLEN = 1101 14 bits for the AD7467
SLEN = 1011 12 bits for the AD7468