Datasheet
AD7452
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a 1.6 V voltage
level. See Figure 2 and the Serial Interface section.
V
DD
= 2.7 V to 3.6 V, f
SCLK
= 10 MHz, f
S
= 555 kSPS, V
REF
= 2.0 V; V
DD
= 4.75 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 555 kSPS, V
REF
= 2.5 V;
V
CM
1
= V
REF A MIN MAX
; T = T to T , unless otherwise noted.
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
2
10 kHz min
10 MHz max
t
CONVERT
16 × t
SCLK
t
SCLK
= 1/f
SCLK
1.6 µs max
t
QUIET
60 ns min
Minimum quiet time between the end of a serial read and the next falling edge of
CS
t
1
10 ns min
Minimum
CS
pulse width
t
2
10 ns min
CS
falling edge to SCLK falling edge setup time
t
3
3
20 ns max
Delay from
CS
falling edge until SDATA three-state disabled
t
4
3
40 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK high pulse width
t
6
0.4 t
SCLK
ns min SCLK low pulse width
t
7
10 ns min SCLK edge to data valid hold time
t
8
4
10 ns min SCLK falling edge to SDATA three-state enabled
35 ns max SCLK falling edge to SDATA three-state enabled
t
POWER-UP
5
1 µs max Power-up time from full power-down
t
3
t
2
t
4
t
7
t
8
t
6
t
1
t
5
t
QUIET
t
CONVERT
CS
SCLK
SDAT
A
4 LEADING ZEROS THREE-STATE
12345 13141516
0 0 0 0 DB11 DB10 DB2 DB1 DB0
B
03154-A-002
Figure 2. Serial Interface Timing Diagram
1
Common-mode voltage.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.4 V with VFigure 3
Figure 3.
DD
= 5 V, or 0.4 V or 2.0 V for V
DD
= 3 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
8
, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5
See section. Power-Up Time