Datasheet

AD7452
Rev. B | Page 4 of 28
Parameter Test Conditions/Comments B Version
2
Unit
CONVERSION RATE
Conversion Time 1.6 µs with a 10 MHz SCLK 16 SCLK cycles
Track-and-Hold Acquisition Time
3
Sine wave input 200 ns max
Step input 290 ns max
Throughput Rate 555 kSPS max
POWER REQUIREMENTS
V
DD
Range: 3 V + 20%/–10%;
5 V ± 5% 2.7/5.25 V min/V max
I
DD
9, 10
Normal Mode (Static) SCLK on or off 0.5 mA typ
Normal Mode (Operational) V
DD
= 4.75 V to 5.25 V 1.5 mA max
V
DD
= 2.7 V to 3.6 V 1.2 mA max
Full Power-Down Mode SCLK on or off 1 µA max
Power Dissipation
Normal Mode (Operational) V
DD
= 5 V, 1.55 mW typ for 100 kSPS
9
7.25 mW max
V
DD
= 3 V, 0.64 mW typ for 100 kSPS
9
3.3 mW max
Full Power-Down V
DD
= 5 V, SCLK on or off 5 µW max
V
DD
= 3 V, SCLK on or off 3 µW max
1
Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in and . Figure 23 Figure 24
2
Temperature ranges as follows: B Version: –40°C to +85°C.
3
See section. Terminology
4
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
5
Because the input spans of V
IN+
and V
IN–
are both V
REF
and are 180° out of phase, the differential voltage is 2 × V
REF.
6
The AD7452 is functional with a reference input from 100 mV; for V
DD
= 5 V, the reference can range up to 3.5 V.
7
The AD7452 is functional with a reference input from 100 mV; for V
DD
= 3 V, the reference can range up to 2.2 V.
8
Guaranteed by characterization.
9
See section. Power vs. Throughput Rate
10
Measured with a midscale dc input.