Datasheet

AD7441/AD7451
Rev. D | Page 4 of 24
Parameter Test Conditions/Comments A Version B Version Unit
CONVERSION RATE
Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK cycles
Track-and-Hold Acquisition Time
1
Sine wave input 250 250 ns max
Full-scale step input 290 290 ns max
Throughput Rate 1 1 MSPS max
POWER REQUIREMENTS
V
DD
2.7/5.25 2.7/5.25 V min/max
I
DD
6, 7
Normal Mode (Static) SCLK on or off 0.5 0.5 mA typ
Normal Mode (Operational) V
DD
= 4.75 V to 5.25 V 1.95 1.95 mA max
V
DD
= 2.7 V to 3.6 V 1.45 1.45 mA max
Full Power-Down Mode SCLK on or off 1 1 μA max
Power Dissipation
Normal Mode (Operational) V
DD
= 5 V; 1.55 mW typical for 100 ksps
6
9.25 9.25 mW max
V
DD
= 3 V; 0.6 mW typical for 100 ksps
6
4 4 mW max
Full Power-Down V
DD
= 5 V; SCLK on or off 5 5 μW max
V
DD
= 3 V; SCLK on or off 3 3 μW max
1
See Terminology section.
2
Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3
A small dc input is applied to V
IN–
to provide a pseudo ground for V
IN+
.
4
The AD7451 is functional with a reference input in the range of 100 mV to V
DD
.
5
Guaranteed by characterization.
6
See the Power vs. Throughput Rate section.
7
Measured with a full-scale dc input.