Datasheet

AD7441/AD7451
Rev. D | Page 17 of 24
Timing Example 2
Timing Example 1
Having f
SCLK
= 5 MHz and a throughput rate of 315 kSPS gives a
cycle time of
Having f
SCLK
= 18 MHz and a throughput rate of 1 MSPS gives a
cycle time of
1/Throughput = 1/315,000 = 3.174 μs
1/Throughput = 1/1,000,000 = 1 μs
A cycle consists of
A cycle consists of
t
2
+ 12.5 (1/f
SCLK
) + t
ACQUISITION
= 3.174 μs
t
2
+ 12.5 (1/f
SCLK
) + t
ACQUISITION
= 1 μs
Therefore, if t
2
is 10 ns, then
Therefore, if t
2
= 10 ns, then
10 ns + 12.5 (1/5 MHz) + t
ACQUISITION
= 3.174 μs
t
ACQUISITION
= 664 ns
10 ns + 12.5 (1/18 MHz) + t
ACQUISITION
= 1 μs
t
ACQUISITION
= 296 ns
This 664 ns satisfies the requirement of 290 ns for t
ACQUISITION
.
This 296 ns satisfies the requirement of 290 ns for t
ACQUISITION
.
From Figure 28, t
ACQUISITION
comprises
From Figure 28, t
ACQUISITION
comprises
2.5 (1/f
SCLK
) + t
8
= t
QUIET
2.5 (1/f
SCLK
) + t
8
= t
QUIET
where t
8
= 35 ns. This allows a value of 129 ns for t
QUIET
,
satisfying the minimum requirement of 60 ns.
where t
8
= 35 ns. This allows a value of 122 ns for t
QUIET
,
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
can already be acquired before the conversion is complete, but it
is still necessary to leave 60 ns minimum t
QUIET
between conver-
sions. In Example 2, the signal is fully acquired at approximately
Point C in Figure 28.
t
2
t
8
t
6
t
5
t
CONVERT
CS
SCLK
12345 13141516
12.5(1/ f
SCLK
) t
ACQUISITION
1/THROUGHPUT
t
QUIET
10ns
B C
03153-028
Figure 28. Serial Interface Timing Example