Datasheet

AD7440/AD7450A
Rev. C | Page 22 of 28
Timing Example 1
Having F
SCLK
= 18 MHz and a throughput rate of 1 MSPS gives a
cycle time of
1/Throughput = 1/1,000,000 = 1 μs
A cycle consists of
t
2
+ 12.5(1/F
SCLK
) + t
ACQ
= 1 μs
Therefore, if t
2
= 10 ns
10 ns + 12.5(1/18 MHz) + t
ACQ
= 1 μs
t
ACQ
= 296 ns
This 296 ns satisfies the requirement of 290 ns for t
ACQ
.
From
Figure 40, t
ACQ
comprises
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 35 ns. This allows a value of 122 ns for t
QUIET
,
satisfying the minimum requirement of 60 ns.
Timing Example 2
Having F
SCLK
= 5 MHz and a throughput rate of 315 kSPS gives a
cycle time of
1/Throughput = 1/315,000 = 3.174 μs
A cycle consists of
t
2
+ 12.5(1/F
SCLK
) + t
ACQ
= 3.174 μs
Therefore, if t
2
is 10 ns
10 ns + 12.5(1/5 MHz) + t
ACQ
= 3.174 μs
t
ACQ
= 664 ns
This 664 ns satisfies the requirement of 290 ns for t
ACQ
.
From
Figure 40, t
ACQ
comprises
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 35 ns. This allows a value of 129 ns for t
QUIET,
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 60 ns minimum t
QUIET
between
conversions. In Timing Example 2, the signal should be fully
acquired at approximately Point C in
Figure 40.