Datasheet

AD7440/AD7450A
Rev. C | Page 21 of 28
Sixteen serial clock cycles are required to perform a conversion
and access data from the AD7440/AD7450A.
SERIAL INTERFACE
CS
going low
provides the first leading zero to be read in by the DSP or
microcontroller. The remaining data is then clocked out on the
subsequent SCLK falling edges beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
provides the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge. Once the conversion is
complete and the data has been accessed after the 16 clock
cycles, it is important to ensure that before the next conversion
is initiated, enough time is left to meet the acquisition and
quiet time specifications (see Timing Examples 1 and 2). To
achieve 1 MSPS with an 18 MHz clock for V
Figure 2 and Figure 3 show detailed timing diagrams for the
serial interface of the AD7450A and the AD7440, respectively.
The serial clock provides the conversion clock and also controls
the transfer of data from the devices during conversion.
CS
initiates the conversion process and frames the data transfer.
The falling edge of
CS
puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point. The conversion
requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track on the next SCLK rising edge, as shown at
Point B in
DD
= 3 V and 5 V, an
18-clock burst performs the conversion and leaves enough time
before the next conversion for the acquisition and quiet time.
Figure 2 and Figure 3. On the 16th SCLK falling
edge, the SDATA line goes back into three-state. If the rising
edge of
CS
occurs before 16 SCLKs have elapsed, the conversion
terminates and the SDATA line goes back into three-state.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge; that is, the first rising edge of
SCLK after the
The conversion result from the AD7440/AD7450A is provided
on the SDATA output as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data
stream of the AD7450A consists of four leading zeros followed
by 12 bits of conversion data provided MSB first; the data
stream of the AD7440 consists of four leading zeros, followed
by the 10 bits of conversion data followed by two trailing zeros,
which is also provided MSB first. In both cases, the output
coding is twos complement.
CS
falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
03051-A-040
t
2
t
8
t
6
t
5
t
CONVERT
CS
SCLK
12345 13141516
12.5(1/F
SCLK
) t
ACQUISITION
1/THROUGHPUT
t
QUIET
10ns
B C
Figure 40. Serial Interface Timing Example