Datasheet
REV. 0–4–
AD74111
TIMING CHARACTERISTICS
(AVDD = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 3.3 V ± 10%, f
MCLK
= 12.288 MHz, f
S
= 48 kHz,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter Min Max Unit Comments
MASTER CLOCK AND RESET
t
MH
MCLK High 25 ns
t
ML
MCLK Low 25 ns
t
RES
RESET Low 10 ns
t
RS
DIN Setup Time 5 MCLKS To RESET Rising Edge
1
t
RH
DIN Setup Time 5 MCLKS To RESET Rising Edge
1
SERIAL PORT
t
CH
DCLK High
2
20 ns
t
CL
DCLK Low
2
20 ns
t
FD
DFS Delay 5 ns From DCLK Rising Edge
3
t
FS
DFS Setup Time 5 ns To DCLK Falling Edge
t
FH
DFS Hold Time 15 ns From DCLK Falling Edge
t
DD
DOUT Delay 30 ns From DCLK Rising Edge
t
DS
DIN Setup Time 5 ns To DCLK Falling Edge
t
DH
DIN Hold Time 15 ns From DCLK Falling Edge
t
DT
DOUT Three-State 40 ns From DCLK Rising Edge
4
NOTES
1
Determines Master/Slave mode operation.
2
Applies in Slave mode only.
3
Applies in Master mode only.
4
Applies in Multiframe-Sync mode only.
MCLK
t
MH
RESET
t
ML
t
RES
t
RS
t
RH
DIN
Figure 1. MCLK and
RESET
Timing
MSB MSB–1
t
FS
DFS
DCLK
DIN
DOUT
MSB MSB–2
MSB–1
MSB–2
t
FH
t
FD
t
DD
t
CH
t
CL
t
DS
t
DH
Figure 2. Serial Port Timing
100A
I
OL
100A
I
OH
C
L
50pF
TO OUTPUT
PIN
DVDD1
2
Figure 3. Load Circuit for Digital Output Timing Specifications