Datasheet

AD7401
Rev. D | Page 4 of 20
Parameter Y Version
1, 2
Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD2
− 0.1 V min I
O
= −200 μA
Output Low Voltage, V
OL
0.4 V max I
O
= +200 μA
POWER REQUIREMENTS
V
DD1
4.5/5.25 V min/V max
V
DD2
3/5.5 V min/V max
I
DD1
6
12 mA max V
DD1
= 5.25 V
I
DD2
7
8 mA max V
DD2
= 5.5 V
4 mA max V
DD2
= 3.3 V
1
Temperature range is −40°C to +85°C.
2
All voltages are relative to their respective ground.
3
See the section. Terminology
4
For f
MCLK
> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V
DD1
= V
DD2
= 5 V ± 5%, and T
A
= −40°C to +85°C.
5
Sample tested during initial release to ensure compliance.
6
See . Figure 15
7
See . Figure 17
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.25 V, V
DD2
= 3 V to 5.5 V, T
A
= T
MAX
to T
MIN
, unless otherwise noted.
1
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
MCLKIN
2, 3
20 MHz max Master clock input frequency
5 MHz min Master clock input frequency
t
1
4
25 ns max Data access time after MCLK rising edge
t
2
4
15 ns min Data hold time after MCLK rising edge
t
3
0.4 × t
MCLKIN
ns min Master clock low time
t
4
0.4 × t
MCLKIN
ns min Master clock high time
1
Sample tested during initial release to ensure compliance
2
Mark space ratio for clock input is 40/60 to 60/40 for f
MCLKIN
to 16 MHz and 48/52 to 52/48 for f
MCLKIN
> 16 MHz to 20 MHz.
3
V
DD1
= V
DD2
= 5 V ± 5% for f
MCLKIN
> 16 MHz to 20 MHz.
4
Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2
200µA I
OL
200µA I
OH
1.6V
T
O OUTPUT
PIN
C
L
25pF
05851-002
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
MDAT
t
1
t
2
t
4
t
3
05851-003
Figure 3. Data Timing