Datasheet

AD7401A
Rev. C | Page 5 of 20
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
f
MCLKIN
2, 3
20 MHz max Master clock input frequency
5 MHz min Master clock input frequency
t
1
4
25 ns max Data access time after MCLKIN rising edge
t
2
4
15 ns min Data hold time after MCLKIN rising edge
t
3
0.4 × t
MCLKIN
ns min Master clock low time
t
4
0.4 × t
MCLKIN
ns min Master clock high time
1
Sample tested during initial release to ensure compliance.
2
Mark space ratio for clock input is 40/60 to 60/40 for f
MCLKIN
≤ 16 MHz and 48/52 to 52/48 for 16 MHz < f
MCLKIN
< 20 MHz.
3
V
DD1
= V
DD2
= 5 V ± 5% for f
MCLKIN
> 16 MHz to 20 MHz.
4
Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
25pF
07332-002
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
MDAT
t
1
t
2
t
4
t
3
07332-003
Figure 3. Data Timing