Datasheet

AD7401A
Rev. C | Page 4 of 20
Y Version
1, 2
Parameter
Min Typ Max
Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD2
− 0.1 V I
O
= −200 μA
Output Low Voltage, V
OL
0.4 V I
O
= +200 μA
POWER REQUIREMENTS
V
DD1
4.5 5.5 V
V
DD2
3 5.5 V
I
DD1
5
10 12 mA V
DD1
= 5.5 V
I
DD2
6
7 9 mA V
DD2
= 5.5 V
3 4 mA V
DD2
= 3.3 V
POWER DISSIPATION (SEE Figure 17)
93.5 MW V
DD1
= V
DD2
= 5.5 V
1
For f
MCLK
> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V
DD1
= V
DD2
= 5 V ± 5%, and T
A
= −40°C to +85°C.
2
All voltages are relative to their respective ground.
3
See the section. Terminology
4
Sample tested during initial release to ensure compliance.
5
See . Figure 15
6
See . Figure 17