Datasheet

AD7398/AD7399
Rev. C | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02179-005
1
V
OUT
B
16
V
OUT
C
2
V
OUT
A
15
V
OUT
D
3
V
SS
14
V
DD
4
V
REF
A
13
V
REF
C
5
V
REF
B
12
V
REF
D
6
GND
11
SDI
7
LDAC
10
CLK
8
RS
9
CS
AD7398/
AD7399
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Table 5. Control Logic Truth Table
CS
CLK
LDAC
Serial Shift Register Function Input Register Function DAC Register
H X H No effect No effect No effect
L L H No effect No effect No effect
L
↑+
H Shift register data advanced one bit Latched No effect
L H H No effect Latched No effect
↑+
L/H H No effect Updated with shift register contents No effect
H X L No effect Latched Transparent
H X
↑+
No effect Latched Latched
NOTES
1. ↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all zeros.
3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out
of shutdown mode.
4. The
LDAC
input is a level-sensitive input that controls the four DAC registers.
Pin No. Mnemonic Description
1 V
OUT
B DAC B Voltage Output.
2 V
OUT
A DAC A Voltage Output.
3 V
SS
Negative Power Supply Input. Specified range of operation 0 V to −5.5 V.
4 V
REF
A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
5 V
REF
B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
6 GND Ground Pin.
7 LDAC Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers.
Asynchronous active low input. See Table 5 for operation.
8 RS Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged.
9 CS Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input
register when CS returns high. Does not effect LDAC operation.
10 CLK Schmitt Triggered Clock Input. Positive edge clocks data into shift register.
11 SDI Serial Data Input. Input data loads directly into the shift register.
12 V
REF
D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
13 V
REF
C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
14 V
DD
Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.
15 V
OUT
D DAC D Voltage Output.
16 V
OUT
C DAC C Voltage Output.