Datasheet

AD7398/AD7399
Rev. C | Page 3 of 24
SPECIFICATIONS
AD7398 12-BIT VOLTAGE OUTPUT DAC
V
DD
= 5 V, V
SS
= 0 V; or V
DD
= + 5 V, V
SS
= −5 V, V
REF
= +2.5 V, −40°C < T
A
< +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Condition 3 V to 5 V ± 10% ±5 V ± 10% Unit
STATIC PERFORMANCE
Resolution
1
N 12 12 Bits
Relative Accuracy
2
INL ±1.5 ±1.5 LSB max
Differential Nonlinearity
2
DNL Monotonic ±1 ±1 LSB max
Zero-Scale Error V
ZSE
Data = 000
H
7 ±2.5 mV max
Full-Scale Voltage Error V
FSE
Data = FFF
H
±2.5 ±2.5 mV max
Full-Scale Tempco
3
TCV
FS
1.5 1.5 ppm/°C typ
REFERENCE INPUT
V
REF
IN Range
4
V
REF
0/V
DD
V
SS
/V
DD
V min/max
Input Resistance
5
R
REF
Data = 555
H
, worst case 35 35 kΩ typ
6
Input Capacitance
3
C
REF
5 5 pF typ
ANALOG OUTPUT
Output Voltage Range V
OUT
0 to V
REF
0 to V
REF
V
Output Current I
OUT
Data = 800
H
, ΔV
OUT
= 4 LSBs ±5 ±5 mA typ
Capacitive Load
3
C
L
No oscillation 200 400 pF max
LOGIC INPUTS
Logic Input Low Voltage V
IL
V
DD
= 3 V 0.5 V max
V
DD
= 5 V 0.8 0.8 V max
Logic Input High Voltage V
IH
CLK only 80% V
DD
4.0 V min
2.1 to 2.4 2.4 V min
Input Leakage Current I
IL
1 1 μA max
Input Capacitance
3
C
IL
10 10 pF max
INTERFACE TIMING
3, 7
Clock Frequency f
CLK
11 16.6 MHz max
Clock Width High t
CH
45 30 ns min
Clock Width Low t
CL
45 30 ns min
CS to Clock Setup
t
CSS
10 5 ns min
Clock to CS Hold
t
CSH
20 15 ns min
Load DAC Pulse Width t
LDAC
45 30 ns min
Data Setup t
DS
15 10 ns min
Data Hold t
DH
10 5 ns min
Load Setup to CS
t
LDS
0 0 ns min
Load Hold to CS
t
LDH
20 15 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000
H
to FFF
H
to 000
H
2 2 V/μs typ
Settling Time
8
t
S
To ±0.1% of full scale 6 6 μs typ
Shutdown Recovery t
SDR
6 6 μs typ
DAC Glitch Q Code 7FF
H
to 800
H
to 7FF
H
150 150 nVs typ
Digital Feedthrough Q
DF
15 15 nVs typ
Feedthrough V
OUT
/V
REF
V
REF
= 1.5 V
DC
1 V p-p, data = 000
H
,
f = 100 kHz
−63 −63 dB typ