Datasheet
AD7398/AD7399
Rev. C | Page 5 of 24
Parameter Symbol Condition 3 V to 5 V ± 10% ±5 V ± 10% Unit
AC CHARACTERISTICS
Output Slew Rate SR Data = 000
H
to 3FF
H
to 000
H
2 2 V/μs typ
Settling Time
8
t
S
To ±0.1% of full scale 6 6 μs typ
Shutdown Recovery t
SDR
6 6 μs typ
DAC Glitch Q Code 1FF
H
to 200
H
to 1FF
H
150 150 nVs typ
Digital Feedthrough Q
DF
15 15 nVs typ
Feedthrough V
OUT
/V
REF
V
REF
= 1.5 V
DC
+ 1 V p-p, −63 −63 dB typ
data = 000
H
, f = 100 kHz
SUPPLY CHARACTERISTICS
Shutdown Supply Current I
DD_SD
No load 30/60 30/60 μA typ/max
Positive Supply Current I
DD
V
IL
= 0 V, no load,
−40°C < T
A
< +125°C
1.5/2.8 1.6/3 mA typ/max
I
DD
V
IL
= 0 V, no load,
−40°C < T
A
< +85°C
1.5/2.6 1.6/2.8 mA typ/max
Negative Supply Current I
SS
V
IL
= 0 V, no load 1.5/2.5 1.6/2.7 mA typ/max
Power Dissipation P
DISS
V
IL
= 0 V, no load 5 16 mW typ
Power Supply Sensitivity PSS ΔV
DD
= ±5% 0.006 0.006 %/% max
1
One LSB = V
REF
/1024 V for the 10-bit AD7399.
2
The first two codes (000
H
and 001
H
) are excluded from the linearity error measurement in single-supply operation.
3
These parameters are guaranteed by design and not subject to production testing.
4
When V
REF
is connected to either the V
DD
or the V
SS
power supply, the corresponding V
OUT
voltage programs between ground and the supply voltage minus the offset
voltage of the output buffer, which is the same as the V
ZSE
error specification. See additional discussion in the Theory of Operation section.
5
Input resistance is code dependent.
6
Typicals represent average readings measured at 25°C.
7
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
TIMING DIAGRAMS
SDI
t
CSS
t
DS
t
DH
t
CH
t
CL
t
CSH
t
LDAC
t
LDH
SA SD A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLK
IN
REG
LD
t
LDS
CS
LDAC
02179-003
Figure 3. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
CLK
t
CH
t
CL
t
CSH
t
CSS
t
LDS
t
LDH
t
LDS
t
LDAC
t
CSS
1/f
CLK
CS
LDAC
02179-004
Figure 4. Continuous Clock Timing Diagram
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