Datasheet
AD7396/AD7397
–6–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No. Name
1V
OUTA
DAC A Voltage Output.
2 AGND Analog Ground.
3 DGND Digital Ground.
4 LDA Load DAC A Register Strobe. Transfers input register data to the DAC A register. Active
low inputs, Level sensitive latch. May be connected together with LDB to double-buffer load
both DAC registers simultaneously.
5 SHDN Power Shutdown Active Low Input. DAC register contents are saved as long as power stays
on the V
DD
pin.
6 RS Resets Input and DAC Register to Zero Condition. Asynchronous active low input.
7–18 D0–D11 Twelve Parallel Input Data Bits. D11 = MSB Pin 18, D0 = LSB Pin 7, AD7396.
7, 8 NC No Connect Pins 7 and 8 On the AD7397 Only.
9–18 D0–D9 Ten Parallel Input Data Bits. D9 = MSB Pin 18, D0 = LSB Pin 9, AD7397 Only.
19 CS Chip Select Latch Enable, Active Low.
20 A/B DAC Input Register Address Select DACA = 1 or DACB = 0.
21 LDB Load DAC B Register Strobe. Transfers input register data to the DAC B register. Active low
inputs, Level sensitive latch. May be connected together with LDA to double-buffer load
both DAC registers simultaneously.
22 V
DD
Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.
23 V
REF
DAC Reference Input Pin. Establishes DAC full-scale voltage.
24 V
OUTB
DAC B Voltage Output.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7396
D5
D4
D3
D2
D1
V
OUTA
AGND
DGND
LDA
D0
RS
SHDN
D6
D7
D8
D9
D10
V
OUTB
V
REF
V
DD
LDB
D11
CS
A/B
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7397
D3
D2
D1
D0
NC
V
OUTA
AGND
DGND
LDA
NC
RS
SHDN
D4
D5
D6
D7
D8
V
OUTB
V
REF
V
DD
LDB
D9
CS
A/B
NC = NO CONNECT