Datasheet

AD7396/AD7397
–4–
REV. 0
Table I. Control Logic Truth
CS A/B LDA LDB RS SHDN Input Register DAC Register
L L HHHX Write to B Latched with Previous Data
L HHHHX Write to A Latched with Previous Data
L L H L H X Write to B B Transparent
L H L H H X Write to A A Transparent
H X L L H X Latched A and B Transparent
H X ^ ^ H X Latched Latched with New Data from Input REG
XXXXLX Reset to Zero Scale Reset to Zero Scale
HXXX^ X Latched to Zero Latched to Zero
^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V
OUTA
and V
OUTB
exhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = “0.”
t
CSW
1 LSB
ERROR BAND
t
AS
t
AH
CS
A/B
t
DH
t
DS
t
LS
t
LH
t
LDW
t
RSW
t
S
t
S
LDA, LDB
RS
V
OUT
D0–D11
Figure 2. Timing Diagram
B REGISTER
1 OF 12
LATCHES
OF THE 2 INPUT
REGISTERS
TO DAC
REGISTERS
DBx
CS
A/B
RS
Figure 3. Digital Control Logic