Datasheet

AD7392/AD7393
Rev. C | Page 5 of 20
TIMING DIAGRAM
0
112 1 - 0 0 4
CS
D11 TO D0
RS
V
OUT
t
CS
DATA VALID
1
0
0
0
1
1
FS
ZS
±0.1%FS
ERROR BAND
t
DS
t
DH
t
RS
t
S
t
S
Figure 2. Timing Diagram