Datasheet

REV. A
–3–
AD7390/AD7391
AD7391 ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions 3 V  10% 5 V  10% Unit
STATIC PERFORMANCE
Resolution
1
N 10 10 Bits
Relative Accuracy
2
INL T
A
= 25°C ±1.75 ±1.75 LSB max
INL T
A
= 40°C, 85°C, 125°C ±2.0 ±2.0 LSB max
INL T
A
= 55°C, S Grade ±3 LSB max
Differential Nonlinearity
2
DNL Monotonic ±0.9 ±0.9 LSB max
DNL T
A
= 55°C, S Grade ±2 LSB max
Zero-Scale Error V
ZSE
Data = 000
H
9.0 9.0 mV max
V
ZSE
T
A
= 55°C, S Grade 20 mV max
Full-Scale Error V
FSE
T
A
= 25°C, 85°C, 125°C, ±32 ±32 mV max
Data = 3FF
H
V
FSE
T
A
= 55°C, S Grade ±55 mV max
Full-Scale Tempco
3
TCV
FS
16 16 ppm/°C typ
TCV
FS
T
A
= 55°C, S Grade 32 ppm/°C typ
REFERENCE INPUT
V
REF IN
Range V
REF
0/V
DD
0/V
DD
V min/max
Input Resistance R
REF
2.5 2.5 MΩ typ
4
Input Capacitance
3
C
REF
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
OUT
Data = 800
H
, ∆V
OUT
= 5 LSB 1 1 mA typ
Output Current (Sink) I
OUT
Data = 800
H
, ∆V
OUT
= 5 LSB 3 3 mA typ
Capacitive Load
3
C
L
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
IL
0.5 0.8 V max
Logic Input High Voltage V
IH
V
DD
 0.6 V
DD
 0.6 V min
Input Leakage Current I
IL
10 10 µA max
Input Capacitance
3
C
IL
10 10 pF max
INTERFACE TIMING
3, 5
Clock Width High t
CH
50 30 ns
Clock Width Low t
CL
50 30 ns
Load Pulsewidth t
LDW
30 20 ns
Data Setup t
DS
10 10 ns
Data Hold t
DH
30 15 ns
Clear Pulsewidth t
CLRW
15 15 ns
Load Setup t
LD1
30 15 ns
Load Hold t
LD2
40 20 ns
AC CHARACTERISTICS
6
Output Slew Rate SR Data = 000
H
to 3FF
H
to 000
H
0.05 0.05 V/µs typ
Settling Time t
S
To 0.1% of Full Scale 70 60 µs typ
t
S
T
A
= –55°C, S Grade 100 µs typ
DAC Glitch Q Code 7FF
H
to 800
H
to 7FF
H
65 65 nVs typ
Digital Feedthrough Q 15 15 nVs typ
Feedthrough V
OUT
/V
REF
V
REF
= 1.5 V
DC
1 V p-p, 63 63 dB typ
Data = 000
H
, f = 100 kHz
SUPPLY CHARACTERISTICS
Power Supply Range V
DD RANGE
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
Positive Supply Current I
DD
V
IL
= 0 V, No Load, T
A
= 25°C55 55 µA typ
I
DD
V
IL
= 0 V, No Load 100 100 µA max
Power Dissipation P
DISS
V
IL
= 0 V, No Load 300 500 µW max
Power Supply Sensitivity PSS ∆V
DD
= ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
REF
/1024 V for the 10-bit AD7391.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
(@ V
REF IN
= 2.5 V, 40  C < T
A
< 85  C unless otherwise noted.)