Datasheet

AD7366/AD7367
Rev. D | Page 7 of 28
TIMING SPECIFICATIONS
AV
CC
= DV
CC
= 4.75 V to 5.25 V, V
DD
= 11.5 V to 16.5 V, V
SS
= −16.5 V to −11.5 V, V
DRIVE
= 2.7 V to 5.25 V, T
A
= −40°C to +85°C,
unless otherwise noted.
1
Table 4.
Parameter
Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
2.7 V ≤ V
DRIVE
< 4.75 V 4.75 V ≤ V
DRIVE
≤ 5.25 V
t
CONVERT
Conversion time, internal clock;
CNVST
falling edge to
BUSY falling edge
680 680 ns max AD7367
610 610 ns max AD7366
f
SCLK
10 10 kHz min Frequency of serial read clock
35 48 MHz max
t
QUIET
30 30 ns min Minimum quiet time required between the end of serial
read and the start of the next conversion
t
1
10 10 ns min Minimum
CNVST
low pulse
t
2
40 40 ns min
CNVST
falling edge to BUSY rising edge
t
3
0 0 ns min BUSY falling edge to MSB, valid when
CS
is low for t
4
prior
to BUSY going low
t
4
10 10 ns max Delay from
CS
falling edge until Pin 1 (D
OUT
A) and Pin 23
(D
OUT
B) are three-state disabled
t
5
2
20 14 ns max Data access time after SCLK falling edge
t
6
7 7 ns min SCLK to data valid hold time
t
7
0.3 × t
SCLK
0.3 × t
SCLK
ns min SCLK low pulse width
t
8
0.3 × t
SCLK
0.3 × t
SCLK
ns min SCLK high pulse width
t
9
10 10 ns max
CS
rising edge to D
OUT
A, D
OUT
B, high impedance
t
POWER-UP
70 70 µs max Power-up time from shutdown mode; time required
between
CNVST
rising edge and
CNVST
falling edge
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology
section, Figure 25, and Figure 26.
2
The time required for the output to cross is 0.4 V or 2.4 V.