Datasheet

AD7366/AD7367
Rev. D | Page 26 of 28
In the example shown in Figure 32, the serial clock is taken
from the ESSI0, so the SCK0 pin must be set as an output
(SCKD = 1) while the SCK1 pin is set as an input (SCKD = 0).
The frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The V
DRIVE
pin of the AD7366/AD7367 takes the same
supply voltage as the power supply pin of the DSP563xx. This
allows the ADC to operate at a higher voltage than its serial
interface and, therefore, the DSP563xx, if necessary.
AD7366/
AD7367*
SCLK
DSP563xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCK0
SC12
SRD1
SRD0
CS
D
OUT
A
D
OUT
B
V
DRIVE
V
DD
SC02
SCK1
IRQ
N
PB
N
CNVST
BUSY
06703-034
Figure 32. Interfacing the AD7366/AD7367 to the DSP563xx