Datasheet

AD7366/AD7367
Rev. D | Page 20 of 28
MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by
the logic state of the
CNVST
signal at the end of a conversion.
There are two possible modes of operation: normal mode and
shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications that require fast
throughput rates. In normal mode, the AD7366/AD7367
remain fully powered at all times, so the user does not need to
worry about power-up times. Figure 22 shows the general mode
of operation of the AD7366 in normal mode; Figure 23 shows
normal mode for the AD7367.
The conversion is initiated on the falling edge of
CNVST
as
described in the Circuit Information section. To ensure that
the part remains fully powered up at all times,
CNVST
must be
at logic state high before the BUSY signal goes low. If
CNVST
is
at logic state low when the BUSY signal goes low, the analog
circuitry powers down and the part ceases converting. The
BUSY signal remains high for the duration of the conversion.
The
CS
pin must be brought low to bring the data bus out of
three-state. Therefore, 12 SCLK cycles are required to read the
conversion result from the AD7366 and 14 SCLK cycles are
required to read the conversion result from the AD7367. The
D
OUT
lines return to three-state only when
CS
is brought high. If
CS
is left low for an additional 12 SCLK cycles for the AD7366 or
14 SCLK cycles for the AD7367, the result from the other on-chip
ADC is also accessed on the same D
OUT
line, as shown in Figure 27
and Figure 28 (see the Serial Interface section).
When 24 SCLK cycles have elapsed for the AD7366 or 28 SCLK
cycles for the AD7367, the D
OUT
line returns to three-state only
when
CS
is brought high, not on the 24
th
or 28
th
SCLK falling
edge. If
CS
is brought high prior to this, the D
OUT
line returns to
three-state at that point. Thus,
CS
must be brought high when
the read is completed, because the bus does not automatically
return to three-state upon completion of the dual result read.
When a data transfer is complete and D
OUT
A and D
OUT
B have
returned to three-state, another conversion can be initiated after
the quiet time, t
QUIET
, has elapsed by bringing
CNVST
low again.
CNVST
BUSY
SCLK
t
2
t
1
t
3
SERIAL READ OPERATION
CS
1
12
t
CONVERT
t
QUIET
06703-024
Figure 22. Normal Mode Operation for the AD7366
BUSY
SCLK
t
2
t
1
t
3
SERIAL READ OPERATION
CS
1
14
t
CONVERT
t
QUIET
06703-025
CNVST
Figure 23. Normal Mode Operation for the AD7367