Datasheet

AD7357
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
V
DD
= 2.5 V ± 10%, V
DRIVE
= 2.25 V to 3.6 V, internal reference = 2.048 V, T
A
= T
MAX
to T
MIN
1
, unless otherwise noted.
Table 3.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
500 kHz min
80 MHz max
t
CONVERT
t
2
+ 15.5 × t
SCLK
ns min t
SCLK
= 1/f
SCLK
t
QUIET
5 ns min
Minimum time between end of serial read and next falling edge of CS
t
2
5 ns min
CS
to SCLK setup time
t
3
2
6 ns max
Delay from CS
until SDATA
A
and SDATA
B
are three-state disabled
t
4
2, 3
Data access time after SCLK falling edge
12.5 ns max 1.8 V ≤ V
DRIVE
< 2.25 V
11 ns max 2.25 V ≤ V
DRIVE
< 2.75 V
9.5 ns max 2.75 V ≤ V
DRIVE
< 3.3 V
9 ns max 3.3 V ≤ V
DRIVE
≤ 3.6 V
t
5
5 ns min SCLK low pulse width
t
6
5 ns min SCLK high pulse width
t
7
2
SCLK to data valid hold time
3.5 ns min 1.8 V ≤ V
DRIVE
< 2.75 V
3 ns min 2.75 V ≤ V
DRIVE
≤ 3.6 V
t
8
9.5 ns max
CS
rising edge to SDATA , SDATA
B
, high impedance
A
t
9
5 ns min
CS
rising edge to falling edge pulse width
t
10
2
4.5 ns min SCLK falling edge to SDATA
A
, SDATA
B
, high impedance
9.5 ns max SCLK falling edge to SDATA
A
, SDATA
B
, high impedance
Latency 1 conversion latency
1
Temperature ranges are as follows: AD7357Y: −40°C to +125°C, AD7357B: −40°C to +85°C, AD7357WY: −40°C to +125°C.
2
Specified with a load capacitance of 10 pF on SDATA
A
and SDATA
B
.
3
The time required for the output to cross 0.4 V or 2.4 V.