Datasheet

AD7352
Rev. A | Page 18 of 20
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial
interfacing to the AD7352. The serial clock provides the
conversion clock and controls the transfer of information
from the AD7352 during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track and hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once
13 SCLK falling edges have elapsed, the track and hold goes
back into track on the next SCLK rising edge, as shown in
at Point B. If a 16-bit data transfer is used on the
AD7352, then two trailing zeros appear after the final LSB. On
the rising edge of
Figure 30
CS
, the conversion is terminated and SDATA
and SDATA
B
go back into three-state. If
A
CS
is not brought high,
but is instead held low for an additional 14 SCLK cycles, the
data from the conversion on ADC B is output on SDATA
A
(see
). Likewise, the data from the conversion on ADC A is
output on SDATA
B
. In this case, the SDATA line in use goes
back into three-state on the 32
nd
SCLK falling edge or the rising
edge of
Figure 31
CS
, whichever occurs first.
A minimum of 14 serial clock cycles is required to perform
the conversion process and to access data from one conversion
on either data line of the AD7352.
CS
falling low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first falling
clock edge on the serial clock has the leading zero provided and
also clocks out the second leading zero. The 12-bit result then
follows with the final bit in the data transfer and is valid on the
14
th
falling edge (having been clocked out on the previous (13
th
)
falling edge). In applications with a slower SCLK, it may be
possible to read in data on each SCLK rising edge, depending
on the SCLK frequency. With a slower SCLK, the first rising
edge of SCLK after the
CS
falling edge has the second leading
zero provided, and the 13
th
rising SCLK edge has DB0 provided.
CS
SCLK
1
5
13
SDATA
A
SDATA
B
2 LEADING ZEROS
THREE-
STATE
t
4
2
34
t
5
t
3
t
QUIET
t
2
THREE-STATE
DB11 DB10 DB2 DB0
t
6
t
7
t
8
00 DB1
B
DB9 DB8
t
9
t
ACQUISITION
t
CONVERT
07044-024
Figure 30. Serial Interface Timing Diagram
CS
SCLK
1
5
15
SDATA
A
THREE-
STATE
t
4
2
34
16
t
5
t
3
t
2
THREE-
STATE
t
6
t
7
14
00 ZERO
DB11
B
17
2 LEADING ZEROS
t
10
32
DB11
A
2 LEADING
ZEROS
DB10
A
DB9
A
ZEROZERO ZERO
2 TRAILING ZEROS
ZERO ZERO
2 TRAILING ZEROS
07044-025
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs