Datasheet

REV. A
AD73360
–7–
t
3
t
2
t
1
Figure 1. MCLK Timing
TO OUTPUT
PIN
+2.1V
100␮A
100␮A
I
OL
I
OH
C
L
15pF
Figure 2. Load Circuit for Timing Specifications
t
3
t
1
t
2
t
13
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
t
4
t
5
t
6
MCLK
SCLK*
Figure 3. SCLK Timing
t
11
t
7
t
9
t
10
t
12
t
7
t
8
SE (I)
SCLK (O)
SDIFS (I)
SDI (I)
SDOFS (O)
SDO (O)
THREE-
STATE
THREE-
STATE
THREE-
STATE
D15 D2 D1 D0 D14
D15D1D14D15
D15
t
8
D0
Figure 4. Serial Port (SPORT)
V
IN
– dBm0
–85 5–75 –65 –55 –45 –35 –25 –15 –5
80
70
–10
S/(N+D) – dB
30
20
10
0
50
40
60
3.17
Figure 5a. S/(N+D) vs. V
IN
(ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
V
IN
– dBm0
–85 5–75 –65 –55 –45 –35 –25 –15 –5
80
70
–10
S/(N+D) – dB
30
20
10
0
50
40
60
3.17
Figure 5b. S/(N+D) vs. V
IN
(ADC @ 5 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)