Datasheet

AD73322
–9–REV. B
TIMING CHARACTERISTICS
Limit at
Parameter T
A
= –40ⴗC to +85ⴗC Units Description
Clock Signals See Figure 1
t
1
61 ns min MCLK Period
t
2
24.4 ns min MCLK Width High
t
3
24.4 ns min MCLK Width Low
Serial Port See Figures 3 and 4
t
4
t
1
ns min SCLK Period
t
5
0.4 × t
1
ns min SCLK Width High
t
6
0.4 × t
1
ns min SCLK Width Low
t
7
20 ns typ SDI/SDIFS Setup Before SCLK Low
t
8
0 ns typ SDI/SDIFS Hold After SCLK Low
t
9
10 ns typ SDOFS Delay from SCLK High
t
10
10 ns typ SDOFS Hold After SCLK High
t
11
10 ns typ SDO Hold After SCLK High
t
12
10 ns typ SDO Delay from SCLK High
t
13
30 ns typ SCLK Delay from MCLK
Specifications subject to change without notice.
(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; AGND = DGND = 0 V; T
A
= T
MlN
to T
MAX
, unless
otherwise noted)
t
3
t
2
t
1
Figure 1. MCLK Timing
t
11
t
7
t
9
t
10
t
7
t
8
t
8
SE (I)
SCLK (O)
SDIFS (I)
SDI (I)
SDOFS (O)
SDO (O)
THREE-
STATE
THREE-
STATE
THREE-
STATE
D15 D2D1D0 D14
D15D0D1D14D15
D15
t
12
Figure 4. Serial Port (SPORT)
t
3
t
1
t
2
t
13
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
t
4
t
5
t
6
MCLK
SCLK*
Figure 3. SCLK Timing
TO OUTPUT
PIN
+2.1V
100mA
100mA
I
OL
I
OH
C
L
15pF
Figure 2. Load Circuit for Timing Specifications