Datasheet

AD73322
–8–
REV. B
Table III. Signal Ranges
3 V Power Supply 5 V Power Supply
5VEN = 0 5VEN = 0 5VEN = 1
VREFCAP 1.2 V ± 10% 1.2 V 2.4 V
VREFOUT 1.2 V ± 10% 1.2 V 2.4 V
ADC Maximum Input Range
at V
IN
1.578 V p-p 1.578 V p-p 3.156 V p-p
Nominal Reference Level 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p
DAC Maximum Voltage
Output Swing
Single-Ended 1.578 V p-p 1.578 V p-p 3.156 V p-p
Differential 3.156 V p-p 3.156 V p-p 6.312 V p-p
Nominal Voltage
Output Swing
Single-Ended 1.0954 V p-p 1.0954 V p-p 2.1908 V p-p
Differential 2.1909 V p-p 2.1909 V p-p 4.3818 V p-p
Output Bias Voltage VREFOUT VREFOUT VREFOUT
TIMING CHARACTERISTICS
Limit at
Parameter T
A
= –40ⴗC to +85ⴗC Units Description
Clock Signals See Figure 1
t
1
61 ns min MCLK Period
t
2
24.4 ns min MCLK Width High
t
3
24.4 ns min MCLK Width Low
Serial Port See Figures 3 and 4
t
4
t
1
ns min SCLK Period
t
5
0.4 × t
1
ns min SCLK Width High
t
6
0.4 × t
1
ns min SCLK Width Low
t
7
20 ns min SDI/SDIFS Setup Before SCLK Low
t
8
0 ns min SDI/SDIFS Hold After SCLK Low
t
9
10 ns max SDOFS Delay from SCLK High
t
10
10 ns min SDOFS Hold After SCLK High
t
11
10 ns min SDO Hold After SCLK High
t
12
10 ns max SDO Delay from SCLK High
t
13
30 ns max SCLK Delay from MCLK
Specifications subject to change without notice.
(AVDD = +3 V ⴞ 10%; DVDD = +3 V ⴞ 10%; AGND = DGND = 0 V; T
A
= T
MlN
to T
MAX
, unless
otherwise noted)