Datasheet

AD73322
–21–REV. B
Table XIV. Control Register A Description
CONTROL REGISTER A
76543210
TESER2CD1CD0CDBLSBLDMM
/ATAD
MGP
Bit Name Description
0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)
1 MM Mixed Mode (0 = Off; 1 = Enabled)
2 DLB Digital Loop-Back Mode (0 = Off; 1 = Enabled)
3 SLB SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
4 DC0 Device Count (Bit 0)
5 DC1 Device Count (Bit 1)
6 DC2 Device Count (Bit 2)
7 RESET Software Reset (0 = Off; 1 = Initiates Reset)
Table XV. Control Register B Description
CONTROL REGISTER B
76 54321 0
CEE MCD2 MCD1 MCD0 SCD1 SCD0 DIR1 DIR0
Bit Name Description
0 DIR0 Decimation/Interpolation Rate (Bit 0)
1 DIR1 Decimation/Interpolation Rate (Bit 1)
2 SCD0 Serial Clock Divider (Bit 0)
3 SCD1 Serial Clock Divider (Bit 1)
4 MCD0 Master Clock Divider (Bit 0)
5 MCD1 Master Clock Divider (Bit 1)
6 MCD2 Master Clock Divider (Bit 2)
7 CEE Control Echo Enable (0 = Off; 1 = Enabled)
Table XVI. Control Register C Description
CONTROL REGISTER C
76 54321 0
5VEN RU PUREF PUDAC PUADC PUIA PUAGT PU
Bit Name Description
0 PU Power-Up Device (0 = Power-Down; 1 = Power On)
1 PUAGT Analog Gain Tap Power (0 = Power-Down; 1 = Power On)
2 PUIA Input Amplifier Power (0 = Power-Down; 1 = Power On)
3 PUADC ADC Power (0 = Power-Down; 1 = Power On)
4 PUDAC DAC Power (0 = Power-Down; 1 = Power On)
5 PUREF REF Power (0 = Power-Down; 1 = Power On)
6 RU REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
7 5VEN Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)