Datasheet

AD73311
–7–
REV. B
t
1
t
2
t
3
Figure 1. MCLK Timing
TIMING CHARACTERISTICS
Limit at
Parameter T
A
= –40ⴗC to +85ⴗC Unit Description
Clock Signals See Figure 1
t
1
61 ns min MCLK Period
t
2
24.4 ns min MCLK Width High
t
3
24.4 ns min MCLK Width Low
Serial Port See Figures 3 and 4
t
4
t
1
ns min SCLK Period
t
5
0.4 × t
1
ns min SCLK Width High
t
6
0.4 × t
1
ns min SCLK Width Low
t
7
20 ns typ SDI/SDIFS Setup Before SCLK Low
t
8
0 ns typ SDI/SDIFS Hold After SCLK Low
t
9
10 ns typ SDOFS Delay from SCLK High
t
10
10 ns typ SDOFS Hold After SCLK High
t
11
10 ns typ SDO Hold After SCLK High
t
12
10 ns typ SDO Delay from SCLK High
t
13
30 ns typ SCLK Delay from MCLK
(AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; AGND = DGND = 0 V; T
A
= T
MlN
to T
MAX
, unless
otherwise noted)
100␮AI
OL
100␮AI
OH
C
L
15pF
+2.1V
TO OUTPUT
PIN
Figure 2. Load Circuit for Timing Specifications
t
1
t
2
t
3
t
13
t
5
t
6
t
4
MCLK
SCLK
*
SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY
(
MCLK/4 SHOWN HERE
)
.
*
Figure 3. SCLK Timing