Datasheet

AD73311
–34–
REV. B
APPENDIX E
DAC Timing Control Example
The AD73311’s DAC is loaded from the DAC register contents
just before the ADC register contents are loaded to the serial
register (SDOFS going high). This default DAC load position
can be advanced in time to occur earlier with respect to the
SDOFS going high. Figure 37 shows an example of the ADC
unload and DAC load sequence. At time t
1
the SDOFS is raised
to indicate that a new ADC word is ready. Following the SDOFS
pulse, 16 bits of ADC data are clocked out on SDO in the sub-
sequent 16 SCLK cycles finishing at time t
2
where the DSP’s
SPORT will have received the 16-bit word. The DSP may
ADC WORD
DAC WORD
SE
SCLK
SDOFS
SDO
SDIFS
SDI
DAC REGISTER
UPDATE
DAC LOAD
FROM DAC REGISTER
t
6
t
4
t
5
t
3
t
2
t
1
Figure 37. DAC Timing Control
process this information and generate a DAC word to be sent to
the AD73311. Time t
3
marks the beginning of the sequence of
sending the DAC word to the AD73311. This sequence ends at
time t
4
where the DAC register will be updated from the 16 bits
in the AD73311’s serial register. However, the DAC will not be
updated from the DAC register until time t
5
which may not be
acceptable in certain applications. In order to reduce this delay
and load the DAC at time t
6
, the DAC advance register can be
programmed with a suitable setting corresponding to the
required time advance (refer to Table VIII for details of DAC
Timing Control settings).