Datasheet

AD73311
–10–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic Function
1 VOUTP Analog Output from the Positive Terminal of the Output Channel.
2 VOUTN Analog Output from the Negative Terminal of the Output Channel.
3 AVDD1 Analog Power Supply Connection for the Output Driver.
4 AGND1 Analog Ground Connection for the Output Driver.
5 VINP Analog Input to the Positive Terminal of the Input Channel.
6 VINN Analog Input to the Negative Terminal of the Input Channel.
7 REFOUT Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent
on the status of Bit 5VEN (CRC:7).
8 REFCAP A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should
be fixed to this pin.
9 AVDD2 Analog Power Supply Connection.
10 AGND2 Analog Ground/Substrate Connection.
11 DGND Digital Ground/Substrate Connection.
12 DVDD Digital Power Supply Connection.
13 RESET Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
14 SCLK Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock
data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to
the frequency of the master clock (MCLK) divided by an integer number—this integer number being
the product of the external master clock rate divider and the serial clock rate divider.
15 MCLK Master Clock Input. MCLK is driven from an external clock signal.
16 SDO Serial Data Output of the Codec. Both data and control information may be output on this pin and is
clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted
and when SE is low.
17 SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one-bit wide and it is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
18 SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and is ignored when SE is low.
19 SDI Serial Data Input of the Codec. Both data and control information may be input on this pin and are
clocked on the negative edge of SCLK. SDI is ignored when SE is low.
20 SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled
internally in order to decrease power dissipation. When SE is brought high, the control and data regis-
ters of the SPORT are at their original values (before SE was brought low), however the timing
counters and other internal registers are at their reset values.