Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 16 Bit SSOP 20

REV. B

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AD73311

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2000

Low Cost, Low Power CMOS

General Purpose Analog Front End

FUNCTIONAL BLOCK DIAGRAM

AD73311

AGND1

AGND2

DGND

DVDD

AVDD2AVDD1

VINP

VINN

VOUTP

VOUTN

REFCAP

REFOUT

SDI

SDIFS

SCLK

SDO

SDOFS

MCLK

RESET

1-BIT

DAC

REFERENCE

SERIAL

I/O

PORT

INTERPOLATOR

DECIMATOR

SWITCHED-

CAPACITOR

LOW-PASS FILTER

CONTINUOUS

TIME

LOW-PASS FILTER

+6/–15dB

PGA

0/38dB

PGA

ANALOG

SIGMA-DELTA

MODULATOR

DIGITAL

SIGMA-DELTA

MODULATOR

FEATURES

16-Bit A/D Converter

16-Bit D/A Converter

Programmable Input/Output Sample Rates

75 dB ADC SNR

70 dB DAC SNR

64 kS/s Maximum Sample Rate

–90 dB Crosstalk

Low Group Delay (25 ␮s Typ per ADC Channel,

50 ␮s Typ per DAC Channel)

Programmable Input/Output Gain

Flexible Serial Port which Allows up to 8 Devices

to Be Connected in Cascade

Single (+2.7 V to +5.5 V) Supply Operation

50 mW Max Power Consumption at 2.7 V

On-Chip Reference

20-Lead SOIC/SSOP Package

APPLICATIONS

General Purpose Analog I/O

Speech Processing

Cordless and Personal Communications

Telephony

Active Control of Sound & Vibration

Data Communications

GENERAL DESCRIPTION

The AD73311 is a complete front-end processor for general

purpose applications including speech and telephony. It features

a 16-bit A/D conversion channel and a 16-bit D/A conversion

channel. Each channel provides 70 dB signal-to-noise ratio over

a voiceband signal bandwidth. The final channel bandwidth can

be reduced, and signal-to-noise ratio improved, by external

digital filtering in a DSP engine.

The AD73311 is suitable for a variety of applications in the

speech and telephony area including low bit rate, high quality

compression, speech enhancement, recognition and synthesis.

The low group delay characteristic of the part makes it suitable

for single or multichannel active control applications.

The gains of the A/D and D/A conversion channels are pro-

grammable over 38 dB and 21 dB ranges respectively. An

on-chip reference voltage is included to allow single supply

operation. A serial port (SPORT) allows easy interfacing of

single or cascaded devices to industry standard DSP engines.

The AD73311 is available in both 20-lead SOIC and SSOP

packages.

Summary of content (36 pages)

PAGE 1
a Low Cost, Low Power CMOS General Purpose Analog Front End AD73311 FEATURES 16-Bit A/D Converter 16-Bit D/A Converter Programmable Input/Output Sample Rates 75 dB ADC SNR 70 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain Flexible Serial Port which Allows up to 8 Devices to Be Connected in Cascade Single (+2.7 V to +5.5 V) Supply Operation 50 mW Max Power Consumption at 2.
PAGE 2
= +3 V ⴞ 10%; DVDD = +3 V ⴞ 10%; DGND = AGND = 0 V, f AD73311–SPECIFICATIONS1 (AVDD F = 64 kHz; T = T to T , unless otherwise noted) MCLK = 16.384 MHz, S Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance Min A AD73311A Typ PGA = 38 dB 1.08 1.08 1 1.2 50 1.32 68 1.2 1.32 100 1.578 –2.85 1.0954 –6.02 –0.75 –1.5 0.1 –0.5 ± 0.
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AD73311 Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection Min AD73311A Typ Group Delay4, 5 Output DC Offset 2, 7 Minimum Load Resistance, R L2, 8 Single-Ended Differential Maximum Load Capacitance, CL2, 8 Single-Ended Differential FREQUENCY RESPONSE (ADC AND DAC)9 Typical Output 0 Hz 2000 Hz 4000 Hz 8000 Hz 12000 Hz 16000 Hz 20000 Hz 24000 Hz 28000 Hz > 32000 Hz LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance LOGIC OUTPUT VOH, Output H
PAGE 4
= +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; DGND = AGND = 0 V, f AD73311–SPECIFICATIONS1 (AVDD F = 64 kHz; T = T to T , unless otherwise noted) MCLK = 16.384 MHz, S A MIN MAX AD73311A Parameter Min REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Typ Max Unit Test Conditions/Comments 1.2 2.4 50 V V ppm/°C 5VEN = 0 5VEN = 1 0.
PAGE 5
AD73311 Parameter Min AD73311A Typ Max Unit Test Conditions/Comments –55 dB Group Delay4, 5 25 µs Output DC Offset 2, 7 Minimum Load Resistance, R L2, 8 Single-Ended Differential Maximum Load Capacitance, CL2, 8 Single-Ended Differential +30 mV Input Signal Level at AVDD and DVDD Pins: 1.
PAGE 6
AD73311 Table II. Current Summary (AVDD = DVDD = +5.5 V) Conditions ADC On Only ADC and DAC On REFCAP On Only REFCAP and REFOUT On Only All Sections Off All Sections Off Analog Current 8.5 14.5 0.8 Internal Digital Current 6 6 0 External Interface Current 2 2 0 Total Current 16.5 22.5 1.0 SE 1 1 0 MCLK ON YES YES NO 3.5 0 0 1.5 0 0 3.5 1.7 0 0 NO YES 0 0.01 0 0.
PAGE 7
AD73311 (AVDD = +5 V ⴞ 10%; DVDD = +5 V ⴞ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) TIMING CHARACTERISTICS Parameter Limit at TA = –40ⴗC to +85ⴗC Unit Description Clock Signals t1 t2 t3 61 24.4 24.4 ns min ns min ns min See Figure 1 MCLK Period MCLK Width High MCLK Width Low Serial Port t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t1 0.4 × t1 0.
PAGE 8
AD73311 SE (I) THREESCLK (O) STATE t7 SDIFS (I) t8 t8 t7 SDI (I) D15 THREESDOFS (O) STATE SDO (O) t9 D14 D1 D15 D0 t10 THREESTATE t11 t12 D15 D2 D1 D15 D0 D14 80 80 70 70 60 60 50 50 S/(N+D) – dB S/(N+D) – dB Figure 4. Serial Port (SPORT) 40 30 30 20 20 10 10 0 0 –10 –85 –75 –65 –55 –45 –35 VIN – dBm0 –25 –15 –10 –85 –5 0 70 70 60 60 50 50 S/(N+D) – dB 80 40 30 10 10 0 0 –55 –45 –35 VIN – dBm0 –25 –15 –45 –35 VIN – dBm0 –25 –15 –5 0 3.
PAGE 9
AD73311 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (TA = +25°C unless otherwise noted) AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . .–0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . .
PAGE 10
AD73311 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function 1 2 3 4 5 6 7 VOUTP VOUTN AVDD1 AGND1 VINP VINN REFOUT 8 REFCAP 9 10 11 12 13 AVDD2 AGND2 DGND DVDD RESET 14 SCLK 15 16 MCLK SDO 17 SDOFS 18 SDIFS 19 SDI 20 SE Analog Output from the Positive Terminal of the Output Channel. Analog Output from the Negative Terminal of the Output Channel. Analog Power Supply Connection for the Output Driver. Analog Ground Connection for the Output Driver.
PAGE 11
AD73311 TERMINOLOGY Absolute Gain ABBREVIATIONS ADC Analog-to-Digital Converter. ALB Analog Loop-Back. BW Bandwidth. CRx A Control Register where x is a placeholder for an alphabetic character (A–E). There are five read/ write control registers on the AD73311—designated CRA through CRE. CRx:n A bit position, where n is a placeholder for a numeric character (0–7), within a control register; where x is a placeholder for an alphabetic character (A–E).
PAGE 12
AD73311 FUNCTIONAL DESCRIPTION Encoder Channel The encoder channel consists of a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest.
PAGE 13
AD73311 at 0x7FFF, which has the LSB set to 1. In mixed Control/Data Mode, the resolution is fixed at 15 bits, with the MSB of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. VINN VREF + (VREF x 0.32875) FB = 4kHz FSINIT = DMCLK/8 ANALOG INPUT a. Analog Antialias Filter Transfer Function SIGNAL TRANSFER FUNCTION VREF VREF – (VREF x 0.32875) VINP 10...00 NOISE TRANSFER FUNCTION FB = 4kHz 00...00 01...
PAGE 14
AD73311 Analog Smoothing Filter & PGA SPORT Overview The output of the single-bit DAC is sampled at DMCLK/8, therefore it is necessary to filter the output to reconstruct the low frequency signal. The decoder’s analog smoothing filter consists of a continuous-time filter preceded by a third-order switched-capacitor filter. The continuous-time filter forms part of the output programmable gain amplifier (PGA).
PAGE 15
AD73311 MCLK (EXTERNAL) MCLK DIVIDER DMCLK (INTERNAL) 3 RESETB SCLK SCLK DIVIDER SERIAL PORT (SPORT) SE SDOFS SDIFS SDI SDO SERIAL REGISTER 2 8 8 8 8 CONTROL REGISTER A CONTROL REGISTER B 8 CONTROL REGISTER C CONTROL REGISTER E CONTROL REGISTER D Figure 9. SPORT Block Diagram SPORT Register Maps Serial Clock Rate Divider There are two register banks for the AD73311: the control register bank and the data register bank.
PAGE 16
AD73311 Table IX. Control Register Map Address (Binary) Name Description Type Width Reset Setting (Hex) 000 001 010 011 100 101 to 111 CRA CRB CRC CRD CRE Control Register A Control Register B Control Register C Control Register D Control Register E Reserved R/W R/W R/W R/W R/W 8 8 8 8 8 0x00 0x00 0x00 0x00 0x00 OPERATION Resetting the AD73311 The pin RESET resets all the control registers.
PAGE 17
AD73311 Table XI. Control Register A Description CONTROL REGISTER A 7 6 5 4 3 2 1 0 RESET DC2 DC1 DC0 DLB ALB MM DATA/ PGM Bit Name Description 0 1 2 3 4 5 6 7 DATA/PGM MM ALB DLB DC0 DC1 DC2 RESET Operating Mode (0 = Program; 1 = Data Mode) Mixed Mode (0 = Off; 1 = Enabled) Analog Loop-Back Mode (0 = Off; 1 = Enabled) Digital Loop-Back Mode (0 = Off; 1 = Enabled) Device Count (Bit 0) Device Count (Bit 1) Device Count (Bit 2) Software Reset (0 = Off; 1 = Initiates Reset) Table XII.
PAGE 18
AD73311 Table XIV. Control Register D Description 7 6 5 4 3 2 1 0 MUTE OGS2 OGS1 OGS0 RMOD IGS2 IGS1 IGS0 CONTROL REGISTER D Bit Name Description 0 1 2 3 4 5 6 7 IGS0 IGS1 IGS2 RMOD OGS0 OGS1 OGS2 MUTE Input Gain Select (Bit 0) Input Gain Select (Bit 1) Input Gain Select (Bit 2) Reset ADC Modulator (0 = Off; 1 = Reset Enabled) Output Gain Select (Bit 0) Output Gain Select (Bit 1) Output Gain Select (Bit 2) Output Mute (0 = Mute Off; 1 = Mute Enabled) Table XV.
PAGE 19
AD73311 Program (Control) Mode In Program Mode, CRA:0 = 0, the user writes to the control registers to set up the device for desired operation—SPORT operation, cascade length, power management, input/output gain, etc. In this mode, the 16-bit information packet sent to the device by the DSP engine is interpreted as a control word whose format is shown in Table X. In this mode, the user must address the device to be programmed using the address field of the control word.
PAGE 20
AD73311 SE SCLK SDOFS SDO SAMPLE WORD (DEVICE 1) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 1) SDIFS SDI Figure 10. Interface Signal Timing for Single Device Operation SE SCLK SDOFS(2) SDO(2) SAMPLE WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) SDOFS(1) SDIFS(2) SDO(1) SDI(2) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) DATA (CONTROL) WORD (DEVICE 1) Figure 11.
PAGE 21
AD73311 INTERFACING Cascade Operation The AD73311 can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompanying frame synchronization signal which is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous.
PAGE 22
AD73311 Control Register A contains a 3-bit field (DC0–2) that is programmed by the DSP during the programming phase. The default condition is that the field contains 000b, which is equivalent to a single device in cascade (see Table XVII). However, for cascade operation this field must contain a binary value that is one less than the number of devices in the cascade.
PAGE 23
AD73311 In order to produce a direct sampling rate of 8 kHz, it is necessary to reduce the external master clock to 8.192 MHz and to set the master clock divider to a ratio of 4, which results in a sample rate of 8 kHz. In this case, the response of the Sinc3 decimation filter may affect the response in the voice BW as its first null occurs at 8 kHz.
PAGE 24
AD73311 It is also possible to subsample the DAC—update at a lower rate than the sampling rate—to reduce the overhead on the DSP. This, however, results in imaging of the subsampled bandwidth into the normal bandwidth, which implies that higher performance external anti-imaging filtering must be used to eliminate the images. The interpolator input also provides a minimum group delay realization in situations where that is critical.
PAGE 25
AD73311 Figures 24 and 25 detail dc- and ac-coupled input circuits for single-ended operation respectively. 100⍀ VINP 0.047␮F VINN VIN Figure 27 shows an example circuit for providing a single-ended output with ac coupling. The capacitor of this circuit (COUT) is not optional if dc current drain is to be avoided. AD73311 AD73311 COUT VOUTP (VOUT CHANNEL) RL VOUTN REFOUT REFCAP 0.1␮F VOLTAGE REFERENCE Figure 27. Example Circuit for Single-Ended Output Digital Interfacing Figure 24.
PAGE 26
AD73311 Cascade Operation Grounding and Layout Where it is required to configure a cascade of up to eight devices, it is necessary to ensure that the timing of the SE and RESET signals is synchronized at each device in the cascade. A simple D type flip flop is sufficient to sync each signal to the master clock MCLK, as in Figure 30. Since the analog inputs to the AD73311 are differential, most of the voltages in the analog modulator are common-mode voltages.
PAGE 27
AD73311 Good decoupling is important when using high speed devices. All analog and digital supplies should be decoupled to AGND and DGND respectively, with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum capacitors. To achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against it.
PAGE 28
AD73311 APPENDIX A Programming a Single AD73311 for Data Mode Operation This section describes a typical sequence in programming a single codec to operate in normal DATA mode. It details the control (program) words that are sent to the device to configure its internal registers and shows the typical output data received during both program and data modes.
PAGE 29
AD73311 APPENDIX B Programming a Single AD73311 for Mixed Mode Operation This section describes a typical sequence in programming a single codec to operate in mixed mode. The device is connected in Nonframe Sync Loop-Back Mode (see Figure 14), which allows the DSP’s Tx Reg to determine how many words are sent to the device. In Step 1, the part has just been reset and on the first output event the codec presents an invalid output word1.
PAGE 30
AD73311 In Step 5, following transmission of the first of the two control words, the DSP Rx register contains Device 2’s ADC word, Device 2’s serial register contains the Device 1 ADC word, Device 1’s serial register contains the control word addressed to Device 2 and the DSP Tx register contains the next control word—that addressed to Device 1. Again, both devices raise their SDOFS lines as both have received control words not addressed to them.
PAGE 31
AD73311 DSP TX REG DEVICE 1 DEVICE 2 DSP RX REG CONTROL WORD 2 1 0 001 001 00000011 ADC WORD 1 * 0000 0000 0000 0000 ADC WORD 2 * 0000 0000 0000 0000 DON'T CARE XXXX XXXX XXXX XXXX STEP 1 DSP TX REG DEVICE 1 DEVICE 2 DSP RX REG CONTROL WORD 1 1 0 000 001 00000011 CONTROL WORD 2 1 0 001 001 00000011 ADC WORD 1 * 0000 0000 0000 0000 ADC WORD 2 * 0000 0000 0000 0000 DSP RX REG STEP 2 DSP TX REG DEVICE 1 DEVICE 2 CONTROL WORD 2 1 0 001 000 00010001 CONTROL WORD 1 1 0 000 001 00000011 CON
PAGE 32
AD73311 APPENDIX D Configuring a Cascade of Two AD73311s to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73311s to configure them for operation in mixed mode. It is not intended to be a definitive initialization sequence, but will show users the typical input/ output events that occur in the programming and operation phases1. This description panel refers to Figure 36.
PAGE 33
AD73311 DSP TX REG DEVICE 1 DEVICE 2 DSP RX REG CONTROL WORD 2 1 0 001 000 00010011 ADC WORD 1 * 0000 0000 0000 0000 ADC WORD 2 * 0000 0000 0000 0000 DON'T CARE XXXX XXXX XXXX XXXX STEP 1 DSP TX REG DEVICE 1 DEVICE 2 DSP RX REG CONTROL WORD 1 1 0 000 000 00010011 CONTROL WORD 2 1 0 001 000 00010011 ADC WORD 1 * 0000 0000 0000 0000 ADC WORD 2 * 0000 0000 0000 0000 STEP 2 DSP TX REG DEVICE 1 DEVICE 2 DSP RX REG CONTROL WORD 2 1 0 001 010 00000001 CONTROL WORD 1 1 0 000 000 00010011 CONTR
PAGE 34
AD73311 APPENDIX E DAC Timing Control Example The AD73311’s DAC is loaded from the DAC register contents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be advanced in time to occur earlier with respect to the SDOFS going high. Figure 37 shows an example of the ADC unload and DAC load sequence. At time t1 the SDOFS is raised to indicate that a new ADC word is ready.
PAGE 35
AD73311 Topic Page FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS (3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 SPECIFICATIONS (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 4, 5 TIMING CHARACTERISTICS (3 V) . . . . . . . . . . . . . . . . . 6 TIMING CHARACTERISTICS (5 V) . . . . . . . . . . . . . .
PAGE 36
AD73311 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Shrink Small Outline IC (RS-20) 0.295 (7.50) 0.271 (6.90) 0.5118 (13.00) 0.4961 (12.60) 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 1 10 0.212 (5.38) 0.205 (5.21) 11 0.0291 (0.74) ⴛ 45ⴗ 0.0098 (0.25) 0.07 (1.78) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 8ⴗ 0.0500 (1.27) 0.0500 0.0192 (0.49) 0ⴗ 0.0157 (0.40) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23) 0.008 (0.203) 0.002 (0.050) 0.