Datasheet

AD7329 Data Sheet
Rev. B | Page 18 of 40
Figure 26 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (see Figure 27). The output
impedances of the source driving the V
IN
+ and V
IN
− pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
CA
P
ACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COM
P
ARA
TOR
SW3
SW1
A
B
C
S
C
S
V
IN
+
SW2
A
B
V
IN
–
V
REF
05402-025
Figure 26. ADC Configuration During Acquisition Phase, Differential Mode
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
ARAT
OR
SW3
SW1
A
B
C
S
C
S
V
IN
+
SW2
A
B
V
IN
–
V
REF
05402-026
Figure 27. ADC Configuration During Conversion Phase, Differential Mode
OUTPUT CODING
The AD7329 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range Full-Scale Range/8192 Codes LSB Size
±10 V 20 V 2.441 mV
±5 V 10 V 1.22 mV
±2.5 V 5 V 0.61 mV
0 V to +10 V 10 V 1.22 mV
The ideal transfer characteristic for the AD7329 when twos
complement coding is selected is shown in Figure 28. The ideal
transfer characteristic for the AD7329 when straight binary
coding is selected is shown in Figure 29.
0
11 ...
11
1
0
11 ...
1
10
000 ... 001
000 ... 000
11
1 ... 11
1
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
AGND – 1LSB
ANALOG INPUT
ADC CODE
100 ... 010
100 ... 001
100 ... 000
05402-027
Figure 28. Twos Complement Transfer Characteristic, Bipolar Ranges
111 ...
111
11
1 ... 110
111 ... 000
011 ... 111
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
ANALOG INPUT
ADC CODE
000 ... 010
000 ... 001
000 ... 000
05402-028
Figure 29. Straight Binary Transfer Characteristic, Bipolar Ranges
ANALOG INPUT STRUCTURE
The analog inputs of the AD7329 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits, as shown in Table 12. The AD7329 can accept
true bipolar input signals. On power-up, the analog inputs operate
as eight single-ended analog input channels. If true differential
or pseudo differential is required, a write to the control register
is necessary after power-up to change this configuration.
Figure 30 shows the equivalent analog input circuit of the
AD7329 in single-ended mode. Figure 31 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
D
D
V
DD
ADC
IN
+MUX
OUT
+
C2
R1
V
IN
0
V
SS
C1
C3
C4
05402-029
Figure 30. Equivalent Analog Input Circuit, Single-Ended Mode