Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 24

1 MSPS, 8-Channel, Software-Selectable,

True Bipolar Input, 12-Bit Plus Sign ADC

Data Sheet

AD7329

Rev. B Document Feedback

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FEATURES

12-bit plus sign SAR ADC

True bipolar input ranges

Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V

1 MSPS throughput rate

8 analog input channels with channel sequencer

Single-ended true differential and pseudo differential

analog input capability

High analog input impedance

MUX

OUT

and ADC

pins allow separate access to mux and ADC

Low power: 21 mW

Temperature indicator

Full power signal bandwidth: 20 MHz

Internal 2.5 V reference

High speed serial interface

iCMOS process technology

24-lead TSSOP package

Power-down modes

FUNCTIONAL BLOCK DIAGRAM

AD7329

AGNDV

DRIVE

DIN

SCLK

DOUT

REF

/REF

OUT

ADC

– ADC

MUX

OUT

+ MUX

OUT

–

T/H

CHANNEL

SEQUENCER

13-BIT SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC AND

REGISTERS

I/P

MUX

2.5V

VREF

05402-001

Figure 1.

GENERAL DESCRIPTION

The AD7329

is an 8-channel, 12-bit plus sign successive

approximation ADC designed on the iCMOS™ (industrial

CMOS) process. iCMOS is a process combining high voltage

CMOS and low voltage CMOS. It enables the development of

a wide range of high performance analog ICs capable of 33 V

operation in a footprint that no previous generation of high

voltage parts could achieve. Unlike analog ICs using conventional

CMOS processes, iCMOS components can accept bipolar input

signals while providing increased performance, dramatically

reduced power consumption, and reduced package size.

The AD7329 can accept true bipolar analog input signals. The

AD7329 has four software-selectable input ranges: ±10 V, ±5 V,

±2.5 V, and 0 V to +10 V. Each analog input channel can be

independently programmed to one of the four input ranges.

The analog input channels on the AD7329 can be programmed

to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7329 also

allows for external reference operation. If a 3 V reference is

applied to the REF

/REF

OUT

pin, the AD7329 can accept a true

bipolar ±12 V analog input. The ADC has a high speed serial

interface that can operate at throughput rates up to 1 MSPS.

PRODUCT HIGHLIGHTS

1. The AD7329 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential input pairs, four pseudo

differential inputs, or seven pseudo differential inputs.

3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 21 mW, at 1 MSPS.

5. The MUX

OUT

± and ADC

± pins allow for signal conditioning

of the mux output prior to entering the ADC.

Table 1. Similar Devices

Device

Number Throughput Rate Number of Channels

AD7328 1000 kSPS 8

AD7327 500 kSPS 8

AD7324 1000 kSPS 4

AD7323 500 kSPS 4

AD7322 1000 kSPS 2

AD7321

500 kSPS

Protected by U.S. Patent No. 6,731,232.

Summary of content (41 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 1 MSPS throughput rate 8 analog input channels with channel sequencer Single-ended true differential and pseudo differential analog input capability High analog input impedance MUXOUT and ADCIN pins allow separate access to mux and ADC Low power: 21 mW Temperature indicator Full power signal bandwidth: 20 MHz Internal 2.
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AD7329 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Addressing Registers .................................................................. 25 Functional Block Diagram .............................................................. 1 Control Register ......................................................................... 26 General Description .....................................................................
PAGE 4
Data Sheet AD7329 SPECIFICATIONS VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN, unless otherwise noted. MUXOUT+ is connected directly to ADCIN+ and MUXOUT− is connected directly to ADCIN−, which is connected to GND for single-ended mode. Table 2.
PAGE 5
AD7329 Parameter 1 DC ACCURACY 4 Resolution No Missing Codes Data Sheet Min B Version Typ Max 13 12-bit plus sign (13 bits) 11-bit plus sign (12 bits) Integral Nonlinearity2 Differential mode Bits Single-ended/pseudo differential mode ±1.1 ±1 LSB LSB LSB −0.9/+1.5 LSB ±0.
PAGE 6
Data Sheet Parameter 1 ANALOG INPUT Input Voltage Ranges (Programmed via Range Register) AD7329 B Version Typ Min Max Unit Test Conditions/Comments ±10 V Reference = 2.5 V; see Table 6 VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V ±5 ±2.5 0 to 10 V V V ±3.5 ±6 ±5 +3/−5 V V V V nA nA pF pF pF pF pF pF pF pF Pseudo Differential VIN− Input Range DC Leakage Current ±100 3 16 7 10 14.5 10.5 4.0 7.
PAGE 7
AD7329 Parameter 1 CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS VCC VDRIVE Normal Mode (Static) Normal Mode (Operational) IDD ISS ICC and IDRIVE Autostandby Mode (Dynamic) IDD ISS ICC and IDRIVE Autoshutdown Mode (Static) IDD ISS ICC and IDRIVE Full Shutdown Mode IDD ISS ICC and IDRIVE POWER DISSIPATION Normal Mode (Operational) Data Sheet Min B Version Typ 12 −12 2.7 2.
PAGE 8
Data Sheet AD7329 TIMING SPECIFICATIONS VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. MUXOUT+ is connected directly to ADCIN+ and MUXOUT− is connected directly to ADCIN−, which is connected to GND for single-ended mode. Table 3.
PAGE 9
AD7329 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
PAGE 10
Data Sheet AD7329 CS 1 24 SCLK DIN 2 23 DGND DGND 3 22 DOUT AGND 4 AD7329 21 VDRIVE TOP VIEW (Not to Scale) 20 VCC 19 VDD REFIN/REFOUT 5 VSS 6 ADCIN+ 7 18 ADCIN– MUXOUT+ 8 17 MUXOUT– VIN0 9 16 VIN2 VIN1 10 15 VIN3 VIN4 11 14 VIN6 VIN5 12 13 VIN7 05402-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No.
PAGE 11
AD7329 Data Sheet Pin No. 17 Mnemonic MUXOUT− 18 ADCIN− 9, 10, 16, 15, 11, 12, 14, 13 VIN0 to VIN7 Descriptions Negative Multiplexer Output. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still a high voltage signal when the AD7329 is in differential mode. When the AD7329 is in single-ended mode, this signal is AGND, and MUXOUT− can be connected directly to the ADCIN− pin.
PAGE 12
Data Sheet AD7329 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0 –40 –60 –80 INL ERROR (LSB) –20 SNR (dB) VCC = VDRIVE = 5V 0.8 TA = 25°C VDD = 15V, VSS = –15V 0.6 4096 POINT FFT VCC = VDRIVE = 5V VDD = 15V, VSS = –15V TA = 25°C INT/EXT 2.5V REFERENCE ±10V RANGE fIN = 50kHz SNR = 77.30dB SINAD = 76.85dB THD = –86.96dB SFDR = –88.22dB INT/EXT 2.5V REFERENCE ±10V RANGE +INL = +0.55LSB –INL = –0.68LSB 0.4 0.2 0 –0.2 –0.4 –100 –0.
PAGE 13
AD7329 Data Sheet –50 80 75 ±2.5V RANGE ±10V RANGE ±5V RANGE 0V TO +10V RANGE 100 0V TO +10V RANGE 1000 ANALOG INPUT FREQUENCY (kHz) Figure 10. THD vs. Analog Input Frequency for Single-Ended Mode at 5 V VCC Figure 13. SINAD vs. Analog Input Frequency for True Differential Mode at 5 V VCC –50 –50 ±5V RANGE –70 0V TO +10V RANGE ±2.
PAGE 14
Data Sheet AD7329 2.0 7600 VCC = 5V VDD = 12V, VSS = –12V RANGE = ±10V 10k SAMPLES TA = 25°C 6k 1.5 5k 4k 3k 0.5 –0.5 INL = 1MSPS –1.0 2k 1201 1165 0 23 –3 –2 1 0 –1 ±5V RANGE VCC = VDRIVE = 5V INTERNAL REFERENCE SINGLE-ENDED MODE AD8021 BETWEEN MUX OUT+ AND ADCIN+ PINS –1.5 11 0 2 3 –2.0 ±5 05402-016 0 CODE ±7 ±9 ±11 ±13 ±15 ±17 ±19 SUPPLY VOLTAGE (V) (VDD = +, VSS = –) Figure 19. INL Error vs. Supply Voltage at 500 kSPS and 1 MSPS Figure 16.
PAGE 15
AD7329 Data Sheet –76 –50 –80 –70 30kHz/500kSPS –75 –84 –85 100 30kHz/1MSPS –86 05402-022 ±2.
PAGE 16
Data Sheet AD7329 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition).
PAGE 17
AD7329 Data Sheet Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. Figure 14 shows the worst case across all eight channels for the AD7329. The analog input range is programmed to be ±2.
PAGE 18
Data Sheet AD7329 THEORY OF OPERATION CIRCUIT INFORMATION The AD7329 is a fast, 8-channel, 12-bit plus sign, bipolar input, serial ADC. The AD7329 can accept bipolar input ranges that include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V unipolar input range. A different analog input range can be programmed on each analog input channel via the on-chip registers. The AD7329 has a high speed serial interface that can operate at throughput rates up to 1 MSPS.
PAGE 19
AD7329 Data Sheet Figure 26 shows the differential configuration during the acquisition phase. For the conversion phase, SW3 opens and SW1 and SW2 move to Position B (see Figure 27). The output impedances of the source driving the VIN+ and VIN− pins must match; otherwise, the two inputs have different settling times, resulting in errors. B CONTROL LOGIC SW3 CS VREF CAPACITIVE DAC 000 ... 001 000 ... 000 111 ... 111 100 ... 010 100 ... 001 100 ... 000 –FSR/2 + 1LSB AGND + 1LSB Figure 26.
PAGE 20
Data Sheet AD7329 For the AD7329, the value of R includes the on resistance of the input multiplexer and is typically 300 Ω. RSOURCE should include any extra source impedance on the analog input. VDD ADCIN+ C1 C3 D C2 C4 The AD7329 enters track mode on the 14th SCLK rising edge. When the AD7329 is run at a throughput rate of 1 MSPS with a 20 MHz SCLK signal, the ADC has approximately 1.5 SCLK periods plus t8 and the quiet time, tQUIET, to acquire the analog input signal.
PAGE 21
AD7329 Data Sheet TYPICAL CONNECTION DIAGRAM ANALOG INPUT Figure 34 shows a typical connection diagram for the AD7329. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7329 can be configured to operate in single-ended, true differential, or pseudo differential mode. The AD7329 can operate with either an internal or external reference.
PAGE 22
Data Sheet AD7329 6 This voltage is set up externally, and its range varies with reference voltage. As the reference voltage increases, the common-mode range decreases. When the differential inputs are driven with an amplifier, the actual common-mode range is determined by the amplifier’s output swing. If the differential inputs are not driven from an amplifier, the common-mode range is determined by the supply voltage on the VDD supply pin and the VSS supply pin.
PAGE 23
AD7329 Data Sheet Pseudo Differential Inputs 8 The AD7329 can have four pseudo differential pairs or seven pseudo differential inputs referenced to a common VIN− pin. The VIN+ inputs are coupled to the signal source and must have an amplitude within the selected range for that channel, as programmed in the range register. A dc input is applied to the VIN− pin. The voltage applied to this input provides an offset for the VIN+ input from ground or pseudo ground.
PAGE 24
Data Sheet AD7329 DRIVER AMPLIFIER CHOICE In applications where the harmonic distortion and signal-tonoise ratio are critical specifications, the analog input of the AD7329 should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier. When no amplifier is used to drive the analog input, the source impedance should be limited to low values.
PAGE 25
AD7329 Data Sheet 1.5kΩ VIN 2kΩ VDD V+ 100nF 1.5kΩ 1.5kΩ 7 MUXOUT+ 1.5kΩ 3 AD8021 1.5kΩ 6 ADCIN+ 5 2 4 V– 10pF 10kΩ VSS Figure 45. Single-Ended-to-Differential Configuration with the AD845 for Bipolar Operation Figure 47. AD8021 Configuration Used Between MUXOUT and ADCIN Pins 442Ω VIN 442Ω AD8021 V+ 442Ω 442Ω 442Ω 442Ω AD8021 05402-043 V– 100Ω 05402-058 05402-042 100nF Figure 46. Single-Ended-to-Differential Configuration with the AD8021 Rev.
PAGE 26
Data Sheet AD7329 REGISTERS The AD7329 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2. These registers are write-only registers. ADDRESSING REGISTERS A serial transfer on the AD7329 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to determine which register is addressed. The three MSBs consist of the write bit, the Register Select 1 bit, and the Register Select 2 bit.
PAGE 27
AD7329 Data Sheet CONTROL REGISTER The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7329 configuration for the next conversion. If the sequence register is being used, data should be loaded into the control register after the range registers and the sequence register have been initialized.
PAGE 28
Data Sheet AD7329 Table 13. Power Mode Selection PM1 1 PM0 1 1 0 0 1 0 0 Description Full shutdown mode. In this mode, all internal circuitry on the AD7329 is powered down. Information in the control register is retained when the AD7329 is in full shutdown mode. Autoshutdown mode. The AD7329 enters autoshutdown on the 15th SCLK rising edge when the control register is updated. All internal circuitry is powered down in autoshutdown. Autostandby mode.
PAGE 29
AD7329 Data Sheet SEQUENCE REGISTER The sequence register on the AD7329 is an 8-bit, write-only register. Each of the eight analog input channels has one corresponding bit in the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
PAGE 30
Data Sheet AD7329 SEQUENCER OPERATION POWER ON. CS DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE FOR EACH ANALOG INPUT CHANNEL. DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V RANGE, SINGLE-ENDED MODE. CS DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE FOR EACH ANALOG INPUT CHANNEL. DOUT: CONVERSION RESULT FROM CHANNEL 0, SINGLE-ENDED MODE, RANGE SELECTED IN RANGE REGISTER 1. CS DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE ANALOG INPUT CHANNELS TO BE INCLUDED IN THE SEQUENCE.
PAGE 31
AD7329 Data Sheet If a change to one of the range registers is required during a sequence, it is necessary to first stop the sequence by writing to the control register and setting SEQ1 to 0 and SEQ2 to 0. Next, write to the range register to change the required range. The previously selected sequence should then be initiated again by writing to the control register and setting SEQ1 to 0 and SEQ2 to 1. The ADC converts the first channel in the sequence.
PAGE 32
Data Sheet AD7329 REFERENCE TEMPERATURE INDICATOR The AD7329 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The internal reference is selected by setting the REF bit in the control register to 1. On power-up, the REF bit is 0, which selects the external reference for the AD7329 conversion. Suitable reference sources for the AD7329 include AD780, AD1582, ADR431, REF193, and ADR391. The AD7329 has an on-chip temperature indicator.
PAGE 33
AD7329 Data Sheet MODES OF OPERATION The AD7329 has several modes of operation that are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. The mode of operation of the AD7329 is controlled by the power management bits, Bit PM1 and Bit PM0, in the control register as shown in Table 13. The default mode is normal mode, where all internal circuitry is fully powered up.
PAGE 34
Data Sheet AD7329 AUTOSHUTDOWN MODE (PM1 = 1, PM0 = 0) AUTOSTANDBY MODE (PM1 = 0, PM0 =1) When the autoshutdown mode is selected, the AD7329 automatically enters shutdown on the 15th SCLK rising edge. In autoshutdown mode, all internal circuitry is powered down. The AD7329 retains information in the registers during autoshutdown. The track-and-hold section is in hold mode during autoshutdown.
PAGE 35
AD7329 Data Sheet POWER VS. THROUGHPUT RATE 20 The power consumption of the AD7329 varies with throughput rate. The static power consumed by the AD7329 is very low, and significant power savings can be achieved as the throughput rate is reduced. Figure 55 and Figure 56 show the power vs. throughput rate for the AD7329 at a VCC of 3 V and 5 V, respectively. Both plots clearly show that the average power consumed by the AD7329 is greatly reduced as the sample frequency is reduced.
PAGE 36
Data Sheet AD7329 SERIAL INTERFACE Figure 57 shows the timing diagram for the serial interface of the AD7329. The serial clock applied to the SCLK pin provides the conversion clock and controls the transfer of information to and from the AD7329 during a conversion. The CS signal initiates the data transfer and the conversion process. The falling edge of CS puts the track-and-hold section into hold mode and takes the bus out of three-state. The analog input signal is then sampled.
PAGE 37
AD7329 Data Sheet MICROPROCESSOR INTERFACING The serial interface on the AD7329 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7329 with some of the most common microcontroller and DSP serial interface protocols. AD7329 TO ADSP-21xx The ADSP-21xx family of DSPs interfaces directly to the AD7329 without requiring glue logic. The VDRIVE pin of the AD7329 takes the same supply voltage as that of the ADSP-21xx.
PAGE 38
Data Sheet AD7329 LAYOUT AND GROUNDING The printed circuit board that houses the AD7329 should be designed so that the analog and digital sections are confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins on the AD7329 should be connected to the AGND plane. Digital and analog ground pins should be joined in only one place.
PAGE 39
AD7329 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 61.
PAGE 40
Data Sheet AD7329 NOTES Rev.