Datasheet

Data Sheet AD7328
Rev. C | Page 29 of 36
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7328 auto-
matically enters shutdown on the 15
th
SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down.
The AD7328 retains information in the registers during
autoshutdown. The track-and-hold is in hold mode during
autoshutdown. On the rising
CS
edge, the track-and-hold,
which was in hold during shutdown, returns to track as the
AD7328 begins to power up. The time to power-up from auto-
shutdown is 500 µs.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15
th
SCLK rising edge.
Figure 50 shows the part entering the autoshutdown mode.
When the AD7328 is in autoshutdown mode, the
CS
signal
must remain low to keep the part in autoshutdown mode. The
AD7328 automatically begins to power up on the
CS
rising edge.
The t
POWER-UP
is required before a valid conversion, initiated by
bringing the
CS
signal low, can take place. After this valid con-
version is complete, the
AD7328 powers down again on the 15
th
SCLK rising edge. The
CS
signal must remain low to keep the
part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 = 1)
In autostandby mode, portions of the AD7328 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to auto-
shutdown but allows the AD7328 to power up much faster,
which allows faster throughput rates.
As is the case with autoshutdown mode, the AD7328 enters
standby on the 15
th
SCLK rising edge when the control register
is updated (see Figure 50). The part retains information in the
registers during standby. The AD7328 remains in standby until
it receives a
CS
rising edge. The ADC begins to power up on the
CS
rising edge. On the
CS
rising edge, the track-and-hold,
which was in hold mode while the part was in standby, returns
to track.
The power-up time from standby is 700 ns. The user should
ensure that 700 ns have elapsed before bringing
CS
low to
attempt a valid conversion. After this valid conversion is
complete, the AD7328 again returns to standby on the 15
th
SCLK rising edge. The
CS
signal must remain low to keep the
part in standby mode.
Figure 50 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby mode.
In Figure 50, the power management bits are configured for auto-
shutdown. For autostandby mode, the power management bits,
PM1 and PM0, should be set to 0 and 1, respectively.
04852-042
CS
1 1615 1 1615
SCLK
SDATA
DIN
VALID DATA VALID DATA
DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER
t
POWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 1, PM0 = 0
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
PART BEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE
t
POWER-UP
HAS ELAPSED
Figure 50. Entering Autoshutdown/Autostandby Mode