Datasheet

AD7328 Data Sheet
Rev. C | Page 28 of 36
MODES OF OPERATION
The AD7328 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7328 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE
(PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate perfor-
mance with the AD7328 being fully powered up at all times.
Figure 48 shows the general operation of the AD7328 in
normal mode.
The conversion is initiated on the falling edge of
CS
, and the track-
and-hold enters hold mode, as described in the Serial Interface
section. The data on the DIN line during the 16 SCLK transfer
is loaded into one of the on-chip registers if the write bit is set.
The register is selected by programming the register select bits
(see Table 8).
1 16
3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RES
ULT
DATA INTO CONTROL/SEQUENCE/RANGE1/
RANGE2
REGISTER
S
CLK
CS
DOUT
DI
N
04852-035
Figure 48. Normal Mode
The AD7328 remains fully powered up at the end of the con-
version if both PM1 and PM0 contain 0 in the control register.
To complete the conversion and access the conversion result
16 serial clock cycles are required. At the end of the conversion,
CS
can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, t
QUIET
, has elapsed.
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7328 is powered
down. The part retains information in the registers during full
shutdown. The AD7328 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the control
register are changed.
A write to the control register with PM1 = PM0 = 1 places the
part into full shutdown mode. The AD7328 enters full shut-
down mode on the 15
th
SCLK rising edge when the control register
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15
th
SCLK rising edge when the control register is updated.
Figure 49 shows how the AD7328 is configured to exit full shut-
down mode. To ensure that the AD7328 is fully powered up,
t
POWER-UP
should elapse before the next
CS
falling edge.
CS
1
16 1 16
SCL
K
SDATA
DI
N
INVAL
ID DATA CHANNE
L IDENTI
FIER BI
TS
+ CON
VERSION RESU
LT
DATA IN
TO CONTR
OL REGISTER DAT
A INTO CONTROL REGI
STER
t
POWER-UP
THE
PART
IS FU
LLY
POW
ERE
D UP
O
NCE
t
PO
WER-
UP
HAS
ELA
PSED
CONTROL REGIST
ER IS LOAD
ED O
N THE FI
RST 15 CLO
CKS,
PM1 = 0, PM0 = 0
T
O KEEP TH
E PART IN N
OR
MAL MODE,
LOAD PM1 = PM0 = 0
IN CONTROL
REGISTER
PART
IS IN
FULL
S
HUTDO
WN
P
ART B
EGINS
TO P
OWE
R UP
ON THE 15TH
SCL
K RI
SING
EDG
E AS
PM1 = PM0 = 0
04852-041
Figure 49. Exiting Full Shutdown Mode