Datasheet

Data Sheet AD7327
Rev. B | Page 17 of 36
Figure 25 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (see Figure 26). The output
impedances of the source driving the V
IN
+ and V
IN
− pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
CAP
ACI
T
IVE
DAC
C
O
NT
R
OL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
C
S
C
S
V
IN
+
SW2
A
B
V
IN
–
V
REF
05401-019
Figure 25. ADC Differential Configuration During Acquisition Phase
CAP
ACIT
IVE
DAC
C
ON
TR
OL
L
OGIC
C
APAC
ITIVE
DA
C
CO
MPA
RAT
OR
S
W3
SW1
A
B
C
S
C
S
V
I
N
+
SW2
A
B
V
IN
–
V
R
E
F
05401-020
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7327 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When operating
in sequence mode, the output coding for each channel in the
sequence is the value written to the coding bit during the last
write to the control register.
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size
is dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range Full-Scale Range/8192 Codes LSB Size
±10 V 20 V 2.441 mV
±5 V 10 V 1.22 mV
±2.5 V
5 V
0.61 mV
0 V to +10 V 10 V 1.22 mV
The ideal transfer characteristic for the AD7327 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7327 when straight binary
coding is selected is shown in Figure 28.
0
1
1
..
.
1
1
1
0
1
1..
.1
1
0
000
...
00
1
000
...
00
0
11
1
...
111
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
AGND – 1LSB
ANALOG INPUT
ADC CODE
100...010
100...001
100...000
05401-021
Figure 27. Twos Complement Transfer Characteristic
1
1
1
...
1
1
1
1
1
1
..
.
1
1
0
1
1
1
...00
0
0
11
..
.1
11
–
F
S
R
/
2 +
1
L
SB
AGND +
1
LSB
+FS
R/2
– 1L
SB B
IP
O
LAR
RANG
ES
+F
S
R –
1
L
S
B
UNI
P
OL
AR RANG
E
ANA
L
OG IN
P
U
T
ADC CODE
000...010
000
...
001
000...
00
0
05401-022
Figure 28. Straight Binary Transfer Characteristic
ANALOG INPUT STRUCTURE
The analog inputs of the AD7327 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 9). The AD7327 can accept true
bipolar input signals. On power-up, the analog inputs operate as
eight single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7327 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
D
D
V
DD
C2
R1
V
IN
0
V
SS
C1
05401-023
Figure 29. Equivalent Analog Input Circuit (Single-Ended)