Datasheet

Data Sheet AD7327
Rev. B | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
2
0
1
9
18
1
7
16
15
1
4
1
3
1
2
1
1
D
I
N
D
GN
D
A
G
N
D
V
IN
0
V
SS
REFIN/OUT
CS
DGND
DOUT
V
DRIVE
V
IN
2
V
DD
V
CC
V
IN
5
V
IN
4
V
IN
1
V
IN
7
V
IN
6
V
IN
3
SCLK
AD7327
TOP VIEW
(Not to Scale)
05401-003
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7327 and frames the serial data transfer.
2 DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
AD7327 on the falling edge of SCLK (see the Registers section).
3, 19 DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7327. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7327. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
5 REFIN/OUT
Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the
AD7327. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor
should be placed on the reference pin (see the Reference section). Alternatively, the internal reference
can be disabled and an external reference applied to this input. On power-up, the external reference
mode is the default condition.
6 V
SS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8, 14, 13, 9,
10, 12, 11
V
IN
0 to V
IN
7
Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the channel address Bit ADD2
through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs,
four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.
The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and
Bit Mode 0, in the control register. The input range on each input channel is controlled by program-
ming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each
analog input channel when a +2.5 V reference voltage is used (see the Registers section).
15 V
DD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
16 V
CC
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7327.
This supply should be decoupled to AGND.
17 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V
CC
,
but it should not exceed V
CC
by more than 0.3 V.
18 DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.
The data is provided MSB first (see the Serial Interface section).
20 SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7327
. This clock is also used as the clock source for the conversion process.