Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 20

500 kSPS, 8-Channel, Software-Selectable,

True Bipolar Input, 12-Bit Plus Sign ADC

Data Sheet

AD7327

Rev. B Document Feedback

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FEATURES

12-bit plus sign SAR ADC

True bipolar input ranges

Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V

500 kSPS throughput rate

8 analog input channels with channel sequencer

Single-ended, true differential, and pseudo differential

analog input capability

High analog input impedance

Low power: 18 mW

Temperature indicator

Full power signal bandwidth: 22 MHz

Internal 2.5 V reference

High speed serial interface

Power-down modes

20-lead TSSOP package

iCMOS™ process technology

FUNCTIONAL BLOCK DIAGRAM

DOUT

SCLK

DIN

DRIVE

REFIN/OUT V

AGND

DGND

CONTROL LOGIC

AND REGISTERS

13-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

2.5V

VREF

I/P

MUX

CHANNEL

SEQUENCER

AD7327

TEMPERATURE

INDICATOR

05401-001

Figure 1.

GENERAL DESCRIPTION

The AD7327

is an 8-channel, 12-bit plus sign successive

approximation ADC designed on the iCMOS (industrial

CMOS) process. iCMOS is a process combining high voltage

silicon with submicron CMOS and complementary bipolar

technologies. It enables the development of a wide range of high

performance analog ICs capable of 33 V operation in a footprint

that no previous generation of high voltage parts could achieve.

Unlike analog ICs using conventional CMOS processes, iCMOS

components can accept bipolar input signals while providing

increased performance, dramatically reduced power

consumption, and reduced package size.

The AD7327 can accept true bipolar analog input signals. The

AD7327 has four software-selectable input ranges: ±10 V, ±5 V,

±2.5 V, and 0 V to +10 V. Each analog input channel can be

independently programmed to one of the four input ranges.

The analog input channels on the AD7327 can be programmed

to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7327 also

allows external reference operation. If a 3 V reference is applied

to the REFIN/OUT pin, the AD7327 can accept a true bipolar

±12 V analog input. Minimum ±12 V V

and V

supplies are

required for the ±12 V input range. The ADC has a high speed

serial interface that can operate at throughput rates up to 500 kSPS.

PRODUCT HIGHLIGHTS

1. The AD7327 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The eight analog inputs can be configured as eight single-

ended inputs, four true differential inputs, four pseudo

differential inputs, or seven pseudo differential inputs.

3. 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 18 mW, at a maximum throughput rate of

500 kSPS.

5. Channel sequencer.

Table 1. Similar Devices

Device

Number

Throughput

Rate Number of bits

Number of

Channels

AD7329

1000 kSPS

12-bit plus sign

AD7328 1000 kSPS 12-bit plus sign 8

AD7324 1000 kSPS 12-bit plus sign 4

AD7323 500 kSPS 12-bit plus sign 4

AD7322 1000 kSPS 12-bit plus sign 2

AD7321 500 kSPS 12-bit plus sign 2

Protected by U.S. Patent No. 6,731,232.

Summary of content (37 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 500 kSPS throughput rate 8 analog input channels with channel sequencer Single-ended, true differential, and pseudo differential analog input capability High analog input impedance Low power: 18 mW Temperature indicator Full power signal bandwidth: 22 MHz Internal 2.
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AD7327 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Sequence Register ....................................................................... 23 Functional Block Diagram .............................................................. 1 Range Registers ........................................................................... 24 General Description ..................................................................
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Data Sheet AD7327 SPECIFICATIONS VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external, fSCLK = 10 MHz, fS = 500 kSPS, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter 1 DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2 Signal-to-Noise + Distortion (SINAD)2 Min B Version Typ Max Unit 76 75.5 72.5 dB dB dB 72 dB 75 dB 74 76 dB dB 72.
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AD7327 Parameter 1 DC ACCURACY 4 Resolution No Missing Codes Data Sheet Min B Version Typ Max 13 12-bit plus sign (13 bits) 11-bit plus sign (12 bits) Test Conditions/Comments Single-ended/pseudo differential mode 1 LSB = FSR/4096, unless otherwise noted. Differential mode 1 LSB = FSR/8192, unless otherwise noted.
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Data Sheet Parameter 1 DC Leakage Current AD7327 B Version Typ Min Reference Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH 2.5 3 ±1 ±5 V µA pF V mV ±10 mV 25 ppm/°C 10 2.5 3 7 0.8 0.4 ±1 10 VDRIVE − 0.2 V 0.4 ±1 5 V V V µA pF VCC = 4.75 V to 5.25 V VCC = 2.7 to 3.
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AD7327 Parameter 1 Autoshutdown Mode (Static) IDD ISS ICC and IDRIVE Full Shutdown Mode IDD ISS ICC and IDRIVE POWER DISSIPATION Normal Mode (Operational) Full Shutdown Mode Data Sheet Min B Version Typ Max Unit 1 1 1 µA µA µA 1 1 1 µA µA µA Test Conditions/Comments SCLK on or off VDD = 16.5 V VSS = −16.5 V VCC/VDRIVE = 5.25 V SCLK on or off VDD = 16.5 V VSS = −16.5 V VCC/VDRIVE = 5.25 V 18 38.25 mW µW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V VDD = +16.5 V, VSS = −16.5 V, VCC = +5.
PAGE 8
Data Sheet AD7327 TIMING SPECIFICATIONS VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external, TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. 1 Table 3.
PAGE 9
AD7327 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
PAGE 10
Data Sheet AD7327 CS 1 20 SCLK DIN 2 19 DGND DGND 3 18 DOUT 17 VDRIVE AGND 4 REFIN/OUT 5 AD7327 TOP VIEW (Not to Scale) 16 VCC VSS 6 15 VDD VIN0 7 14 VIN2 VIN1 8 13 VIN3 VIN4 9 12 VIN6 VIN5 10 11 VIN7 05401-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No.
PAGE 11
AD7327 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0 4096 POINT FFT VCC = VDRIVE = 5V VDD, VSS = ±15V TA = 25°C INT/EXT 2.5V REFERENCE ±10V RANGE FIN = 50kHz SNR = 77.30dB SINAD = 76.85dB THD = –86.96dB SFDR = –88.22dB SNR (dB) –40 –60 –80 0.6 0.4 INL ERROR (LSB) –20 VCC = VDRIVE = 5V INT/EXT 2.5V REFERENCE TA = 25°C ±10V RANGE VDD, VSS = ±15V +INL = +0.55LSB –INL = –0.68LSB 0.8 0.2 0 –0.2 –0.4 –100 –0.6 –120 0 50 100 150 200 250 FREQUENCY (kHz) 05401-004 –1.0 –140 0 Figure 4.
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Data Sheet AD7327 –50 75 ±2.5V SE 70 ±10V SE ±10V DIFF –75 0V TO +10V DIFF –80 ±5V SE 0V TO +10V SE 60 ±2.5V DIFF –90 –100 10 100 1000 ANALOG INPUT FREQUENCY (kHz) 50 10 –50 0V TO +10V SE ±10V SE –70 ±10V DIFF –75 0V TO +10V DIFF –80 ±5V SE –85 ±5V DIFF –90 ±2.5V SE –95 –55 VCC = 3V –60 VCC = 5V –65 –70 –75 –80 VDD/VSS = ±12V SINGLE-ENDED MODE fS = 500kSPS TA = 25°C 50kHz ON SELECTED CHANNEL –85 –90 ±2.
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AD7327 8k 2.0 7600 VCC = 5V VDD/VSS = ±12V RANGE = ±10V 10k SAMPLES TA = 25°C 6k 1.5 1.0 INL ERROR (LSB) 5k 4k 3k 0.5 INL = 500kSPS 0 –0.5 –1.0 1165 0 23 –3 –2 –1 0 11 0 2 3 1 –2.0 05401-014 0 ±5V RANGE VCC = VDRIVE = 5V INTERNAL REFERENCE SINGLE-ENDED MODE –1.5 1k CODE 5 –50 –55 –55 –60 –60 –65 –65 CMRR (dB) PSRR (dB) VCC = 5V –75 VCC = 3V –85 0 200 400 600 800 1000 1200 VCC = 5V VCC = 3V –75 VDD = 12V –80 VSS = –12V 0 200 400 600 800 –50 –55 –60 1.
PAGE 14
Data Sheet AD7327 –50 THD (dB) VCC = VDRIVE = 5V –55 VDD/VSS = ±12V TA = 25°C –60 INTERNAL REF RANGE = ±10V AND ±2.5V –65 fS = 500kSPS SINGLE-ENDED MODE ±10V RANGE RIN = 4000Ω RIN = 2000Ω RIN = 1000Ω RIN = 100Ω RIN = 50Ω –70 –75 ±2.5V RANGE RIN = 4700Ω RIN = 3000Ω RIN = 1000Ω RIN = 100Ω RIN = 50Ω –80 –85 –90 100 INPUT FREQUENCY (kHz) 1000 05401-065 –95 –100 10 Figure 22. THD vs. Analog Input Frequency for Various Source Impedances, Single-Ended Mode Rev.
PAGE 15
AD7327 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition).
PAGE 16
Data Sheet AD7327 Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. Figure 14 shows the worstcase across all eight channels for the AD7327. The analog input range is programmed to be the same on all channels.
PAGE 17
AD7327 THEORY OF OPERATION The AD7327 requires VDD and VSS dual supplies for the high voltage analog input structures. These supplies must be equal to or greater than the analog input range. See Table 6 for the requirements of these supplies for each analog input range. The AD7327 requires a low voltage 2.7 V to 5.25 V VCC supply to power the ADC core. Table 6. Reference and Supply Requirements for Each Analog Input Range Selected Analog Input Range (V) ±10 ±5 ±2.5 0 to +10 1 Reference Voltage (V) 2.5 3.
PAGE 18
Data Sheet AD7327 Figure 25 shows the differential configuration during the acquisition phase. For the conversion phase, SW3 opens and SW1 and SW2 move to Position B (see Figure 26). The output impedances of the source driving the VIN+ and VIN− pins must match; otherwise, the two inputs have different settling times, resulting in errors. A SW1 A SW2 B CONTROL LOGIC SW3 100...010 100...001 100...000 CS VREF CAPACITIVE DAC 000...001 000...000 111...111 –FSR/2 + 1LSB AGND + 1LSB Figure 25.
PAGE 19
AD7327 VDD C1 R1 C2 D 1.5 SCLK + t8 + tQUIET VSS to acquire the analog input signal. The ADC goes back into hold mode on the CS falling edge. C1 D VSS R1 C2 05401-024 D VIN– Figure 30. Equivalent Analog Input Circuit (Differential) Care should be taken to ensure that the analog input does not exceed the VDD and VSS supply rails by more than 300 mV. Exceeding this value causes the diodes to become forward biased and to start conducting into either the VDD supply rail or VSS supply rail.
PAGE 20
Data Sheet AD7327 V+ TYPICAL CONNECTION DIAGRAM Figure 32 shows a typical connection diagram for the AD7327. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7327 can be configured to operate in single-ended, true differential, or pseudo differential mode. The AD7327 can operate with either an internal or external reference.
PAGE 21
AD7327 8 5 ±5V RANGE 6 ±5V RANGE 3 ±2.5V RANGE VCOM RANGE (V) VCOM RANGE (V) 1 0 –2 –3 ±10V RANGE ±2.5V RANGE ±10V RANGE ±10V RANGE 2 0 –2 –4 ±5V RANGE –4 VCC = 3V VREF = 3V –6 05401-045 –5 –6 ±16.5V VDD/VSS ±12V VDD/VSS –8 ±12V VDD/VSS Figure 38. Common-Mode Range for VCC = 5 V and REFIN/OUT = 2.5 V 8 Pseudo Differential Inputs ±5V RANGE 6 VCOM RANGE (V) ±2.5V RANGE VCC = 5V VREF = 2.5V ±16.5V VDD/VSS Figure 35.
PAGE 22
Data Sheet AD7327 6 4 ±5V RANGE ±2.5V RANGE ±10V RANGE The driver amplifier must be able to settle for a full-scale step to a 13-bit level, 0.0122%, in less than the specified acquisition time of the AD7327. An op amp such as the AD8021 meets this requirement when operating in single-ended mode. The AD8021 needs an external compensating NPO type of capacitor. The AD8022 can also be used in high frequency applications where a dual version is required.
PAGE 23
AD7327 REGISTERS The AD7327 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2. These registers are write-only registers. ADDRESSING REGISTERS A serial transfer on the AD7327 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to determine which register is addressed. The three MSBs consist of the write bit, the Register Select 1 bit, and the Register Select 2 bit.
PAGE 24
Data Sheet AD7327 The eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true differential inputs, or eight single-ended analog inputs. Table 10.
PAGE 25
AD7327 RANGE REGISTERS The range registers are used to select one analog input range per analog input channel. Range Register 1 is used to set the ranges for Channel 0 to Channel 3. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. A write to Range Register 1 is selected by setting the write bit to 1 and the register select bits to 0 and 1.
PAGE 26
Data Sheet AD7327 SEQUENCER OPERATION POWER ON. CS DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE FOR EACH ANALOG INPUT CHANNEL. DOUT: CONVERSION RESULT FROM CHANNEL 0, ±10V RANGE, SINGLE-ENDED MODE. CS DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE FOR EACH ANALOG INPUT CHANNEL. DOUT: CONVERSION RESULT FROM CHANNEL 0, SINGLE-ENDED MODE, RANGE SELECTED IN RANGE REGISTER 1. CS DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE ANALOG INPUT CHANNELS TO BE INCLUDED IN THE SEQUENCE.
PAGE 27
AD7327 If a change to one of the range registers is required during a sequence, it is necessary to first stop the sequence by writing to the control register and setting Seq1 to 0 and Seq2 to 0. Next, the write to the range register should be completed to change the required range. The previously selected sequence should then be initiated again by writing to the control register and setting Seq1 to 0 and Seq2 to 1. The ADC converts the first channel in the sequence.
PAGE 28
Data Sheet AD7327 REFERENCE TEMPERATURE INDICATOR The AD7327 can operate with either the internal 2.5 V onchip reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register to 1. On power-up, the Ref bit is 0, which selects the external reference for the AD7327 conversion. Suitable reference sources for the AD7327 include AD780, AD1582, ADR431, REF193, and ADR391. The AD7327 has an on-chip temperature indicator.
PAGE 29
AD7327 MODES OF OPERATION The AD7327 remains fully powered up at the end of the conversion if both PM1 and PM0 contain 0 in the control register. The AD7327 has several modes of operation that are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements.
PAGE 30
Data Sheet AD7327 AUTOSHUTDOWN MODE (PM1 = 1, PM0 = 0) Once the autoshutdown mode is selected, the AD7327 automatically enters shutdown on the 15th SCLK rising edge. In autoshutdown mode, all internal circuitry is powered down. The AD7327 retains information in the registers during autoshutdown. The track-and-hold is in hold mode during autoshutdown. On the rising CS edge, the track-and-hold, which was in hold during autoshutdown, returns to track as the AD7327 begins to power up.
PAGE 31
AD7327 POWER VS. THROUGHPUT RATE 20 16 8 6 VARIABLE SCLK 4 2 100 200 300 400 THROUGHPUT RATE (kSPS) Figure 52. Power vs. Throughput Rate with 5 V VCC 6 VARIABLE SCLK 4 2 0 300 400 THROUGHPUT RATE (kSPS) 500 05401-052 AVERAGE POWER (mW) 10 0 8 200 12 0 VCC = 3V VDD/VSS = ±12V TA = 25°C 10 INTERNAL REFERENCE 100 14 Figure 51. Power vs. Throughput Rate with 3 V VCC Rev.
PAGE 32
Data Sheet AD7327 SERIAL INTERFACE Figure 53 shows the timing diagram for the serial interface of the AD7327. The serial clock applied to the SCLK pin provides the conversion clock and controls the transfer of information to and from the AD7327 during a conversion. Data is clocked into the AD7327 on the SCLK falling edge. The three MSBs on the DIN line are decoded to select which register is addressed. The control register is a 12-bit register.
PAGE 33
AD7327 MICROPROCESSOR INTERFACING The serial interface on the AD7327 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7327 with some common microcontroller and DSP serial interface protocols. AD7327 TO ADSP-21xx The ADSP-21xx family of DSPs interface directly to the AD7327 without requiring glue logic. The VDRIVE pin of the AD7327 takes the same supply voltage as that of the ADSP-21xx.
PAGE 34
Data Sheet AD7327 APPLICATION HINTS LAYOUT AND GROUNDING POWER SUPPLY CONFIGURATION The printed circuit board that houses the AD7327 should be designed so that the analog and digital sections are confined to certain areas of the board. This design facilitates the use of ground planes that can easily be separated. It is recommended that Schottky diodes be placed in series with the AD7327 VDD and VSS supply signals. Figure 56 shows this Schottky diode configuration. BAT43 Schottky diodes are used.
PAGE 35
AD7327 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 10 1 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 57.
PAGE 36
Data Sheet AD7327 NOTES Rev.