Datasheet

AD7324 Data Sheet
Rev. B | Page 32 of 36
MICROPROCESSOR INTERFACING
The serial interface on the AD7324 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7324 with some common
microcontroller and DSP serial interface protocols.
AD7324 TO ADSP-21xx
The ADSP-21xx family of DSPs interface directly to the AD7324
without requiring glue logic. The V
DRIVE
pin of the AD7324 takes
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial
interface. The SPORT0 on the ADSP-21xx should be configured
as shown in Table 14.
Table 14. SPORT0 Control Register Setup
Setting Description
TFSW = RFSW = 1 Alternative framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111 16-bit data word
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 52. The ADSP-21xx
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing
mode, and the SPORT0 control register is set up as described in
Table 14. The frame synchronization signal generated on the
TFS is tied to
CS
and, as with all signal processing applications,
requires equidistant sampling. However, as in this example, the
timer interrupt is used to control the sampling rate of the ADC,
and under certain conditions, equidistant sampling cannot be
achieved.
AD732
4
1
ADSP-21x
x
1
SC
LK
SCLK0
CS
TFS0
RFS0
D
OUT
DIN
DT0
DR0
V
DD
V
DRIVE
1
ADDITIONA
L PINS OMITTED FOR CLARITY.
04864-037
Figure 52. Interfacing the AD7324 to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data.
The frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given (AX0 = TX0),
the state of the serial clock is checked. The DSP waits until the
SCLK has gone high, low, and high again before starting the
transmission. If the timer and SCLK are chosen, so that the
instruction to transmit occurs on or near the rising edge of SCLK,
data can be transmitted immediately or at the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods elapse
for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation leads
to nonequidistant sampling because the transmit instruction
occurs on an SCLK edge. If the number of SCLKs between
interrupts is an integer of N, equidistant sampling is implemented
by the DSP.
AD7324 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interface directly to the
AD7324 without requiring glue logic, as shown in Figure 53.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 15.
AD7324
1
ADSP-BF53x
1
V
DD
V
DRI
VE
SCLK
RS
CLK0
DIN
DT0
DOUT
DR0
CS
RFS0
1
ADDI
TIONA
L PI
NS O
MITTE
D FOR CLARITY.
04864-038
Figure 53. Interfacing the AD7324 to the ADSP-BF53x
Table 15. SPORT0 Receive Configuration 1 Register
Setting Description
RCKFE = 1 Sample data with falling edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00
Zero fill
IRCLK = 1 Internal receive clock
RSPEN = 1 Receive enable
SLEN = 1111 16-bit data-word
TFSR = RFSR = 1