Datasheet

Data Sheet AD7324
Rev. B | Page 31 of 36
SERIAL INTERFACE
Figure 51 shows the timing diagram for the serial interface of
the AD7324. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7324 during a conversion.
The
CS
signal initiates the data transfer and the conversion
process. The falling edge of
CS
puts the track-and-hold into hold
mode and takes the bus out of three-state. Then the analog input
signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
th
SCLK
rising edge. On the 16
th
SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of
CS
occurs before 16 SCLK cycles
have elapsed, the conversion is terminated, and the DOUT line
returns to three-state. Depending on where the
CS
signal is brought
high, the addressed register may be updated.
Data is clocked into the AD7324 on the SCLK falling edge. The
3 MSBs on the DIN line are decoded to select which register is
being addressed. The control register is a 12-bit register. If the
control register is addressed by the 3 MSBs, the data on the DIN
line is loaded into the control on the 15
th
SCLK rising edge. If the
sequence register or the range register is addressed, the data on
the DIN line is loaded into the addressed register on the 11
th
SCLK
falling edge.
Conversion data is clocked out of the AD7324 on each SCLK
falling edge. Data on the DOUT line consists of a leading ZERO
bit, two channel identifier bits, a sign bit, and a 12-bit conversion
result. The channel identifier bits are used to indicate which
channel corresponds to the conversion result. The leading ZERO
bit is clocked out on the
CS
falling edge, and the first channel
identifier bit is clocked out on the first SCLK falling edge.
ADD1
1 2 3 4 5 13 14 15
16
WRITE
REG
SEL1
REG
SEL2
LSBMSB
ADD0 SIGN DB11 DB10 DB2 DB1 DB0
t
2
t
6
t
4
t
9
t
10
t
3
t
7
t
5
t
8
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ZERO
2 IDENTIFICATION BITS
04864-036
DON’T
CARE
Figure 51. Serial Interface Timing Diagram (Control Register Write)