Datasheet

AD7324 Data Sheet
Rev. B | Page 18 of 36
D
D
V
DD
C
2
R
1
V
IN
+
V
S
S
C
1
D
D
V
DD
C
2
R1
V
I
N
–
V
SS
C
1
04864-024
Figure 30. Equivalent Analog Input Circuit (Differential)
Care should be taken to ensure that the analog input does not
exceed the V
DD
and V
SS
supply rails by more than 300 m V.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the V
DD
supply rail or
V
SS
supply rail. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
Track-and-Hold Section
The track-and-hold on the analog input of the AD7324 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The
AD7324 can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14
th
SCLK
rising edge after the
CS
falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With 0 source impedance, 305 ns are
sufficient to acquire the signal to the 13-bit level. The
acquisition time required is calculated using the following
formula:
t
ACQ
= 10 × ((R
SOURCE
+ R) × C)
where C is the sampling capacitance and R is the resistance seen
by the track-and-hold amplifier looking back on the input. For
the AD7324, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. R
SOURCE
should include
any extra source impedance on the analog input.
The AD7324 enters track mode on the 14
th
SCLK rising edge.
When running the AD7324 at a throughput rate of 1 MSPS with
a 20 MHz SCLK signal, the ADC has approximately
1.5 SCLK + t8 + t
QUIET
to acquire the analog input signal. The ADC goes back into
hold mode on the
CS
falling edge.
As the V
DD
/V
SS
supply voltage is reduced, the on resistance of
the input multiplexer increases. Therefore, based on the equation
for t
ACQ
, it is necessary to increase the amount of acquisition
time provided to the AD7324 and, therefore, decrease the overall
throughput rate. Figure 31 shows that if the throughput rate is
reduced when operating with minimum V
DD
and V
SS
supplies,
the specified THD performance is maintained.
–50
–95
5
19
±V
DD
/V
SS
SUPPLIES (V)
THD (dB)
–55
–60
–65
–70
–75
–80
–85
–90
7 9 11 13 15 17
500kSPS
750kSPS
1MSPS
V
CC
= V
DRIVE
= 5V
INTERNAL REFERENCE
T
A
= 25°C
F
IN
= 10kHz
±5V RANGE
SE MODE
04864-051
Figure 31. THD vs. ±V
DD
/V
SS
Supply Voltage at 500 kSPS, 750 kSPS,
and 1 MSPS
Unlike other bipolar ADCs, the AD7324 does not have a
resistive analog input structure. On the AD7324, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7324 high analog input impedance. An
approximation for the analog input impedance can be
calculated from the following formula:
Z = 1/(f
S
× C
S
)
where f
S
is the sampling frequency, and C
S
is the sampling
capacitor value.
C
S
depends on the analog input range chosen (see the
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 75 kΩ for the ±10 V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases the
current required to drive the analog input, therefore, decreases.