Datasheet
Data Sheet AD7323
Rev. B | Page 19 of 36
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7323.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7323 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7323 can operate
with either an internal or external reference. In Figure 32, the
AD7323 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The V
CC
pin can be connected to either a 3 V supply voltage or a
5 V supply voltage. V
DD
and V
SS
are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Tabl e 6). The V
DRIVE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the V
DRIVE
input controls the voltage of
the serial interface. V
DRIVE
can be set to 3 V or 5 V.
AD
7323
V
CC
V
DD
1
SER
I
AL
IN
TERF
ACE
µC
/µP
V
I
N
0
V
IN
1
V
I
N
2
V
I
N
3
R
EF
IN
/OU
T
C
S
D
OU
T
V
DRI
VE
SCLK
DI
N
DGND
10µ
F 0.
1µF
+
10
µ
F0
.1
µ
F
+
10µF
0.1
µF
+
ANALOG INP
UTS
±
10V
,
±5
V,
±2.
5V
0V
TO +
10V
+
15V
–15V
680n
F
V
SS
1
V
CC
+
2
.7
V T
O
5.
25V
1
MINI
MUM V
DD
AND V
SS
SUPP
LY VO
LTAG
ES
DEPEND ON
THE H
IGHEST
ANALOG I
N
PU
T
RANGE SE
LEC
TED
.
AG
ND
10µ
F 0.
1µF
+
+3
V SU
PPLY
05400-025
Figure 32. Typical Connection Diagram
ANALOG INPUT
Single-Ended Inputs
The AD7323 has a total of four analog inputs when operating
the AD7323 in single-ended mode. Each analog input can be
independently programmed to one of the four analog input
ranges. In applications where the signal source is high
impedance, it is recommended to buffer the signal before
applying it to the ADC analog inputs. Figure 33 shows the
configuration of the AD7323 in single-ended mode.
AD7323
1
V
IN
x
V+
V–
V
DD
V
SS
V
CC
5V
AGND
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05400-026
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7323 can have a total of two true differential analog
input pairs. Differential signals have some benefits over single-
ended signals, including better noise immunity based on the
device’s common-mode rejection and improvements in distor-
tion performance. Figure 34 defines the configuration of the
true differential analog inputs of the AD7323.
AD7323
1
V
IN
+
V
IN
–
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05400-027
NOTES
1. V
IN
+ CAN BE V
IN
0 OR V
IN
2, AND V
IN
– CAN BE V
IN
1 OR V
IN
3.
Figure 34. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the V
IN
+ and V
IN
− inputs in
each differential pair (V
IN
+ − V
IN
−). V
IN
+ and V
IN
− should
be simultaneously driven by two signals, each of amplitude
±4 × V
REF
(depending on the input range selected) that are 180°
out of phase. Assuming the ±4 × V
REF
mode, the amplitude of
the differential signal is −20 V to +20 V p-p (2 × 4 × V
REF
),
regardless of the common mode.
The common mode is the average of the two signals
(V
IN
+ + V
IN
−)/2
and is therefore the voltage on which the two input signals are
centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common-mode range is
determined by the amplifier’s output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the V
DD
supply pin
and the V
SS
supply pin.