Datasheet

AD7322 Data Sheet
Rev. B | Page 6 of 36
TIMING SPECIFICATIONS
Unless otherwise noted, V
DD
= 12 V to 16.5 V, V
SS
= −12 V to −16.5 V, V
CC
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25, V
DRIVE
≤ V
CC
,
V
REF
= 2.5 V to 3.0 V internal/external, T
A
= T
MAX
to T
MIN
.
1
Table 3.
Limit at T
MIN
, T
MAX
Parameter V
CC
< 4.75 V V
CC
= 4.75 V to 5.25 V Unit Description
f
SCLK
50
50
kHz min
14 20 MHz max
t
CONVERT
16 × t
SCLK
16 × t
SCLK
ns max t
SCLK
= 1/f
SCLK
t
QUIET
75 60 ns min
Minimum time between end of serial read and next falling edge of
CS
t
1
12 5 ns min
Minimum
CS pulse width
t
2
2
25 20 ns min
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
45 35 ns min Unipolar input range (0 V to 10 V)
t
3
26 14 ns max
Delay from
CS until DOUT three-state disabled
t
4
57 43 ns max Data access time after SCLK falling edge
t
5
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
13
8
ns min
SCLK to data valid hold time
t
8
40 22 ns max SCLK falling edge to DOUT high impedance
10 9 ns min SCLK falling edge to DOUT high impedance
t
9
4 4 ns min DIN setup time prior to SCLK falling edge
t
10
2 2 ns min DIN hold time after SCLK falling edge
t
POWER-UP
750 750 ns max Power up from autostandby
500 500 µs max Power up from full shutdown/autoshutdown mode, internal reference
25 25 µs typ Power up from full shutdown/autoshutdown mode, external reference
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
2
When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t
2
at 20 ns, the mark space ratio must be limited to 50:50.
ZER
O
1
2 3 4 5 13
14 15 16
WRITE
ZERO
REG
SEL
L
SBMSB
ADD0 SIGN DB11 DB10
DB2 DB
1 DB0
t
2
t
6
t
4
t
9
t
1
0
t
3
t
7
t
5
t
8
t
1
t
QUI
ET
t
C
ONVE
RT
SC
LK
CS
D
OUT
THREE-
S
TAT
E
T
HREE-ST
ATE
DIN
Z
ERO
ID
ENT
IFIC
ATIO
N BI
T
04863-002
DON’
T
CARE
Figure 2. Serial Interface Timing Diagram