Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 14

2-Channel, Software-Selectable, True

Bipolar Input, 1 MSPS, 12-Bit Plus Sign ADC

Data Sheet

AD7322

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

12-bit plus sign SAR ADC

True bipolar input ranges

Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V

1 MSPS throughput rate

Two analog input channels with channel sequencer

Single-ended, true differential, and pseudo differential

analog input capability

High analog input impedance

Low power: 21 mW

Full power signal bandwidth: 22 MHz

Internal 2.5 V reference

High speed serial interface

Power-down modes

14-lead TSSOP package

iCMOS process technology

FUNCTIONAL BLOCK DIAGRAM

04863-001

DOUT

SCLK

DIN

DRIVE

REFIN/OUT

AGND V

DGND

CONTROL LOGIC

AND REGISTERS

13-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

2.5V

VREF

I/P

MUX

CHANNEL

SEQUENCER

AD7322

Figure 1.

GENERAL DESCRIPTION

The AD7322

is a 2-channel, 12-bit plus sign, successive approx-

imation analog-to-digital converter (ADC) designed on the

iCMOS™ (industrial CMOS) process. iCMOS is a process

combining high voltage silicon with submicron CMOS and

complementary bipolar technologies. It enables the develop-

ment of a wide range of high performance analog ICs capable of

33 V operation in a footprint that no previous generation of high

voltage parts could achieve. Unlike analog ICs using conventional

CMOS processes, iCMOS components can accept bipolar input

signals while providing increased performance, dramatically

reduced power consumption, and reduced package size.

The AD7322 can accept true bipolar analog input signals. The

AD7322 has four software-selectable input ranges, ±10 V, ± 5 V,

±2.5 V, and 0 V to +10 V. Each analog input channel can be

independently programmed to one of the four input ranges.

The analog input channels on the AD7322 can be programmed

to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7322 also

allows for external reference operation. If a 3 V reference is

applied to the REFIN/OUT pin, the AD7322 can accept a true

bipolar ±12 V analog input. Minimum ±12 V V

and V

supplies are required for the ±12 V input range. The ADC has a

high speed serial interface that can operate at throughput rates

up to 1 MSPS.

PRODUCT HIGHLIGHTS

1. The AD7322 can accept true bipolar analog input signals,

±10 V, ± 5 V, and ±2.5 V, and 0 V to +10 V unipolar signals.

2. The two analog inputs can be configured as two single-

ended inputs, one true differential input, or one pseudo

differential input.

3. 1 MSPS serial interface. SPI-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 31 mW maximum, at 1 MSPS throughput rate.

5. Channel sequencer.

Table 1. Similar Devices

Device

Number

Throughput

Rate Number of bits

Number of

Channels

AD7329 1000 kSPS 12-bit plus sign 8

AD7328 1000 kSPS 12-bit plus sign 8

AD7327 500 kSPS 12-bit plus sign 8

AD7324 1000 kSPS 12-bit plus sign 4

AD7323

500 kSPS

12-bit plus sign

AD7321 500 kSPS 12-bit plus sign 2

Protected by U.S. Patent No. 6,731,232.

Summary of content (37 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 1 MSPS throughput rate Two analog input channels with channel sequencer Single-ended, true differential, and pseudo differential analog input capability High analog input impedance Low power: 21 mW Full power signal bandwidth: 22 MHz Internal 2.
PAGE 2
Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD7322* Last content update 12/22/2013 04:27 pm SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES Find Similar Products By Operating Parameters Low Resolution - Simultaneous Sampling 12-Bit PulSAR ADCs Low Resolution - Muxed 8/10/12/13-Bit PulSAR ADCs DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.
PAGE 3
AD7322 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Register ......................................................................... 22 Functional Block Diagram .............................................................. 1 Range Register ............................................................................ 24 General Description .................................................................
PAGE 4
Data Sheet AD7322 SPECIFICATIONS Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN; for VCC < 4.75 V, all specifications are typical. Table 2. Parameter 1 DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2 Signal-to-Noise + Distortion (SINAD)2 Min B Version Typ Max 76 72.5 75 dB dB dB dB dB 76 72 72.
PAGE 5
AD7322 Parameter 1 Differential Nonlinearity2 Data Sheet Min B Version Typ Max −0.9/+1.5 Unit LSB ±0.9 LSB −0.7/+1 Offset Error2, 4 LSB −4/+9 −7/+10 ±0.6 ±0.5 ±8 ±14 ±0.5 ±0.5 ±4 ±7 ±0.5 ±0.5 ±8.5 ±7.5 ±0.5 ±0.5 ±4 ±6 ±0.5 ±0.
PAGE 6
Data Sheet Parameter 1 LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding AD7322 B Version Typ Min Unit Test Conditions/Comments 0.8 0.4 ±1 V V V µA pF VCC = 4.75 V to 5.25 V VCC = 2.7 V to 3.6 V VIN = 0 V or VDRIVE 0.4 ±1 V V µA pF 2.4 10 VDRIVE − 0.
PAGE 7
AD7322 Data Sheet TIMING SPECIFICATIONS Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25, VDRIVE ≤ VCC, VREF = 2.5 V to 3.0 V internal/external, TA = TMAX to TMIN. 1 Table 3.
PAGE 8
Data Sheet AD7322 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 4.
PAGE 9
AD7322 Data Sheet CS 1 14 SCLK DIN 2 13 DGND DOUT DGND 3 AD7322 12 AGND 4 TOP VIEW (Not to Scale) 11 VDRIVE REFIN/OUT 5 10 VCC VSS 6 9 VDD VIN0 7 8 VIN1 04863-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic CS 2 DIN 3, 13 DGND 4 AGND 5 REFIN/OUT 6 7, 8 VSS VIN0, VIN1 9 10 VDD VCC 11 VDRIVE 12 DOUT 14 SCLK Description Chip Select. Active low logic input.
PAGE 10
Data Sheet AD7322 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0 4096 POINT FFT VCC = VDRIVE = 5V VDD, VSS = ±15V TA = 25°C INT/EXT 2.5V REFERENCE ±10V RANGE fIN = 50kHz SNR = 77.30dB SINAD = 76.85dB THD = –86.96dB SFDR = –88.22dB SNR (dB) –40 –60 –80 0.6 0.4 INL ERROR (LSB) –20 VCC = VDRIVE = 5V INT/EXT 2.5V REFERENCE ±10V RANGE TA = 25°C +INL = +0.55LSB VDD, VSS = ±15V –INL = –0.68LSB 0.8 0.2 0 –0.2 –0.4 –100 –0.
PAGE 11
AD7322 Data Sheet –50 –60 THD (dB) –65 ±10V DIFF ±5V DIFF 75 0V TO +10V DIFF 0V TO +10V SE 70 ±5V SE –70 –75 ±2.5V DIFF ±10V SE ±10V DIFF SINAD (dB) –55 80 VCC = 5V VDD/VSS = ±12V TA = 25°C fS = 1MSPS ±5V DIFF ±2.5V DIFF –80 0V TO +10V SE ±2.5V SE 65 ±10V SE ±5V SE 0V TO +10V DIFF 60 –85 ±2.5V SE VCC = 3V VDD/VSS = ±12V TA = 25°C fS = 1MSPS 55 –95 1000 100 ANALOG INPUT FREQUENCY (kHz) 50 10 04863-008 –100 10 Figure 10. THD vs.
PAGE 12
Data Sheet AD7322 8k 2.0 7600 VCC = 5V VDD/VSS = ±12V RANGE = ±10V 10k SAMPLES TA = 25°C 6k 1.5 INL = 500kSPS 5k 4k 3k INL = 750kSPS –0.5 0 1 11 0 2 3 –2.0 CODE Figure 16. Histogram of Codes, Single-Ended Mode –55 –55 –60 –60 –65 –65 PSRR (dB) VCC = 5V –75 VCC = 3V –85 DIFFERENTIAL MODE fIN = 50kHz VDD/VSS = ±12V fS = 1MSPS TA = 25°C –95 0 200 400 600 800 1000 1200 VCC = 5V VCC = 3V –75 VDD = 12V –80 VSS = –12V 0 –55 DNL = 500kSPS –60 1.
PAGE 13
AD7322 –50 VCC = VDRIVE = 5V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE RANGE = ±10V AND ±2.5V –60 –65 RIN = 2000Ω, ±10V RANGE RIN = 100Ω, ±10V RANGE –70 RIN = 1000Ω, ±10V RANGE RIN = 50Ω, ±10V RANGE –75 RIN = 2000Ω, ±2.5V RANGE –80 RIN = 1000Ω, ±2.5V RANGE –85 RIN = 100Ω, ±2.5V RANGE –90 RIN = 50Ω, ±2.5V RANGE –95 10 100 INPUT FREQUENCY (kHz) 1000 04863-016 –55 THD (dB) Data Sheet Figure 22. THD vs. Analog Input Frequency for Various Source Impedances, Single-Ended Mode Rev.
PAGE 14
Data Sheet AD7322 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition).
PAGE 15
AD7322 Data Sheet Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. Figure 14 shows the worstcase across all eight channels for the AD7322. The analog input range is programmed to be the same on all channels.
PAGE 16
Data Sheet AD7322 THEORY OF OPERATION CIRCUIT INFORMATION The AD7322 is a fast, 2-channel, 12-bit plus sign, bipolar input, serial ADC. The AD7322 can accept bipolar input ranges that include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V unipolar input range. A different analog input range can be programmed on each analog input channel via the on-chip registers. The AD7322 has a high speed serial interface that can operate at throughput rates up to 1 MSPS.
PAGE 17
AD7322 Data Sheet CAPACITIVE DAC B CONTROL LOGIC SW3 100...010 100...001 100...000 CS VREF CAPACITIVE DAC NOTES 1. VIN+ REFERS TO VIN0 AND VIN– REFERS TO VIN1. 000...001 000...000 111...111 –FSR/2 + 1LSB AGND + 1LSB AGND – 1LSB +FSR/2 – 1LSB BIPOLAR RANGES +FSR – 1LSB UNIPOLAR RANGE ANALOG INPUT 04863-021 A SW1 A SW2 04863-019 VIN– COMPARATOR CS B VIN+ 011...111 011...110 ADC CODE Figure 25 shows the differential configuration during the acquisition phase.
PAGE 18
Data Sheet AD7322 VDD VIN+ C1 R1 The AD7322 enters track mode on the 14th SCLK rising edge. When running the AD7322 at a throughput rate of 1 MSPS with a 20 MHz SCLK signal, the ADC has approximately C2 D 1.5 SCLK + t8 + tQUIET VSS to acquire the analog input signal. The ADC goes back into hold mode on the CS falling edge. D VIN– C2 D VSS NOTES 1. VIN+ REFERS TO VIN0 AND VIN– REFERS TO VIN1. 04863-024 C1 R1 Figure 30.
PAGE 19
AD7322 Data Sheet V+ TYPICAL CONNECTION DIAGRAM Figure 32 shows a typical connection diagram for the AD7322. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7322 can be configured to operate in single-ended, true differential, or pseudo differential mode. The AD7322 can operate with either an internal or external reference.
PAGE 20
Data Sheet AD7322 8 When a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude −2 × (4 × VREF) to +2 × (4 × VREF), corresponding to Digital Code −4096 to Digital Code +4095. 6 ±5V RANGE ±2.5V RANGE VCOM RANGE (V) 2 0 –2 –3 ±10V RANGE 2 0 –2 –4 1 –6 ±10V RANGE –1 ±5V RANGE ±2.5V RANGE –8 ±5V RANGE ±2.5V RANGE VCC = 5V VREF = 2.5V ±12V VDD/VSS ±16.5V VDD/VSS ±10V RANGE 04863-048 VCOM RANGE (V) ±5V RANGE 3 ±2.
PAGE 21
AD7322 Data Sheet 6 4 time of the AD7322. An op amp such as the AD8021 meets this requirement when operating in single-ended mode. The AD8021 needs an external compensating NPO type of capacitor. The AD8022 can also be used in high frequency applications where a dual version is required. ±5V RANGE ±5V RANGE ±2.5V RANGE ±10V RANGE ±2.5V RANGE 2 For lower frequency applications, op amps such as the AD797, AD845, and the AD8610 can be used in the AD7322 singleended mode configuration.
PAGE 22
Data Sheet AD7322 REGISTERS on the DIN line following the register select bit loads into the addressed register. If the write bit is 1, the bits are loaded into the register addressed by the register select bits. If the write bit is 0, the data on the DIN line does not load into any register. The zero bit must always be set to 0. The AD7322 has two programmable registers, the control register and the range register. These registers are write-only registers.
PAGE 23
AD7322 Data Sheet CONTROL REGISTER The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7322 configuration for the next conversion. Data should be loaded into the control MSB 15 Write 14 Zero 13 Register Select 12 Zero 11 Zero 10 ADD0 9 Mode 1 register after the range register has been initialized.
PAGE 24
Data Sheet AD7322 Table 11. Power Mode Selection PM1 1 PM0 1 1 0 0 1 0 0 Description Full shutdown mode. In this mode, all internal circuitry on the AD7322 is powered down. Information in the control register is retained when the AD7322 is in full shutdown mode. Autoshutdown mode. The AD7322 enters autoshutdown on the 15th SCLK rising edge when the control register is updated. All internal circuitry is powered down in autoshutdown. Autostandby mode.
PAGE 25
AD7322 Data Sheet RANGE REGISTER register select bit to 1. After the initial write to the range register occurs, each time an analog input is selected, the AD7322 automatically configures the analog input to the appropriate range, as indicated by the range register. The ±10 V input range is selected by default on each analog input channel (see Table 13). The range register is used to select one analog input range per analog input channel.
PAGE 26
Data Sheet AD7322 SEQUENCER OPERATION The AD7322 can be configured to convert a sequence of consecutive channels (see Figure 44). This sequence begins by converting on Channel 0 and ends with a final channel selected by Bit ADD0 in the control register. To operate the AD7322 in this mode, set Seq1 to 1 and Seq2 to 0, and then select the final channel in the sequence by programming Bit ADD0 in the control register.
PAGE 27
AD7322 Data Sheet REFERENCE The AD7322 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register to 1. On power-up, the Ref bit is 0, resulting in the selection of the external reference for the AD7322 conversion. Suitable reference sources for the AD7322 include AD780, AD1582, ADR431, REF193, and ADR391. The internal reference circuitry consists of a 2.
PAGE 28
Data Sheet AD7322 MODES OF OPERATION The AD7322 has several modes of operation that are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. The mode of operation of the AD7322 is controlled by the power management bits, Bit PM1 and Bit PM0, in the control register as shown in Table 11. The default mode is normal mode, in which all internal circuitry is fully powered up.
PAGE 29
AD7322 Data Sheet AUTOSHUTDOWN MODE (PM1 = 1, PM0 = 0) AUTOSTANDBY MODE (PM1 = 0, PM0 = 1) Once the autoshutdown mode is selected, the AD7322 automatically enters shutdown on the 15th SCLK rising edge. In autoshutdown mode, all internal circuitry is powered down. The AD7322 retains information in the registers during autoshutdown. The track-and-hold is in hold mode during autoshutdown.
PAGE 30
Data Sheet AD7322 POWER vs. THROUGHPUT RATE 20 18 16 VARIABLE SCLK 14 20MHz SCLK 12 10 8 6 4 VCC = 5V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE 2 0 0 12 100 200 300 400 500 600 700 800 900 THROUGHPUT RATE (kHz) Figure 49. Power vs. Throughput Rate with 5 V VCC 20MHz SCLK 8 VARIABLE SCLK 6 4 VCC = 3V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE 2 0 0 100 200 300 400 500 600 700 800 900 1000 1100 THROUGHPUT RATE (kSPS) 04863-052 AVERAGE POWER (mW) 10 Figure 48.
PAGE 31
AD7322 Data Sheet SERIAL INTERFACE Data is clocked into the AD7322 on the SCLK falling edge. The three MSBs on the DIN line are decoded to select which register is addressed. The control register is a 12-bit register. If the control register is addressed by the three MSBs, the data on the DIN line is loaded into the control on the 15th SCLK rising edge. If the range register is addressed, the data on the DIN line is loaded into the addressed register on the 11th SCLK falling edge.
PAGE 32
Data Sheet AD7322 MICROPROCESSOR INTERFACING The serial interface on the AD7322 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7322 with some common microcontroller and DSP serial interface protocols. AD7322 TO ADSP-21xx The ADSP-21xx family of DSPs interface directly to the AD7322 without requiring glue logic. The VDRIVE pin of the AD7322 takes the same supply voltage as that of the ADSP-21xx.
PAGE 33
AD7322 Data Sheet APPLICATION HINTS LAYOUT AND GROUNDING POWER SUPPLY CONFIGURATION The printed circuit board that houses the AD7322 should be designed so that the analog and digital sections are confined to certain areas of the board. This design facilitates the use of ground planes that can easily be separated. It is recommended that Schottky diodes be placed in series with the AD7322 VDD and VSS supply signals. Figure 53 shows this Schottky diode configuration. BAT43 Schottky diodes are used.
PAGE 34
Data Sheet AD7322 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 Figure 54.
PAGE 35
AD7322 Data Sheet NOTES Rev.
PAGE 36
Data Sheet AD7322 NOTES Rev.