Datasheet
Data Sheet AD7321
Rev. B | Page 31 of 36
SERIAL INTERFACE
Figure 50 shows the timing diagram for the serial interface of
the AD7321. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7321 during a conversion.
The
CS
signal initiates the data transfer and the conversion
process. The falling edge of
CS
puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. Once the conversion is initiated, it
requires 16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
th
SCLK
rising edge. On the 16
th
SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of
CS
occurs before 16 SCLK cycles
have elapsed, the conversion is terminated, and the DOUT line
returns to three-state. Depending on where the
CS
signal is brought
high, the addressed register may be updated.
Data is clocked into the AD7321 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is being addressed. The control register is a 12-bit register. If the
control register is addressed by the three MSBs, the data on the
DIN line is loaded into the control on the 15
th
SCLK falling
edge. If the range register is addressed, the data on the DIN line is
loaded into the addressed register on the 11
th
SCLK falling edge.
Conversion data is clocked out of the AD7321 on each SCLK
falling edge. Data on the DOUT line consists of two leading
ZEROs, a channel identifier bit, a sign bit, and a 12-bit conversion
result. The channel identifier bit is used to indicate which channel
corresponds to the conversion result. The first ZERO bit is clocked
out on the
CS
falling edge, and the second bit is clocked out on
the first SCLK falling edge.
Z
ER
O
1
2 3
4
5 1
3
14
15
1
6
WR
I
TE
ZER
O
REG
SEL
LSB
DO
N’T
CARE
MSB
ADD0
SIG
N D
B
1
1
DB1
0
DB2
DB
1
DB0
t
2
t
6
t
4
t
9
t
1
0
t
3
t
7
t
5
t
8
t
1
t
Q
U
I
E
T
t
C
O
N
VE
R
T
S
C
LK
C
S
D
OU
T
T
HREE-
ST
A
TE
T
HR
EE-S
TA
T
E
D
I
N
Z
ER
O
I
D
EN
TI
F
IC
A
TIO
N
B
I
T
05399-036
Figure 50. Serial Interface Timing Diagram (Control Register Write)