Datasheet

Data Sheet AD7321
Rev. B | Page 19 of 36
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7321.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7321 are configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7321 can operate
with either an internal or external reference. In Figure 32, the
AD7321 is configured to operate with the internal 2.5 V
reference. A 680 nF decoupling capacitor is required when
operating with the internal reference.
The V
CC
pin can be connected to either a 3 V supply voltage or a
5 V supply voltage. The V
DD
and V
SS
are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6). The V
DRIVE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the V
DRIVE
input controls the voltage of
the serial interface. V
DRIVE
is set to 3 V or 5 V.
AD7321
V
CC
V
DD
1
SERIAL
INTERFACE
µC/µP
V
IN
0
V
IN
1
REFIN/OUT
CS
DOUT
V
DRIVE
SCLK
DIN
DGND
10µF 0.1µF
+
10µF0.1µF
+
10µF0.1µF
+
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
+15V
–15V
680nF
V
SS
1
V
CC
+ 2.7V TO 5.25V
1
MINIMUM V
DD
AND V
SS
SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
10µF 0.1µF
+
+3V SUPPLY
05399-025
Figure 32. Typical Connection Diagram
ANALOG INPUT
Single-Ended Inputs
The AD7321 has a total of two analog inputs when operating
the AD7321 in single-ended mode. Each analog input is
independently programmed to one of the four analog input
ranges. In applications where the signal source is high
impedance, it is recommended to buffer the signal before
applying it to the ADC analog inputs. Figure 33 shows the
configuration of the AD7321 in single-ended mode.
AD7321
1
V
IN
+
V+
V–
V
DD
V
SS
V
CC
5V
AGND
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05399-026
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7321 can have one true differential analog input pair.
Differential signals have some benefits over single-ended
signals, including better noise immunity based on the common-
mode rejection of the device and improvements in distortion
performance. Figure 34 defines the configuration of the true
differential analog inputs of the AD7321.
AD732
1
1
V
IN
+
V
IN
–
1
ADDI
TIONA
L PINS OMITTED FOR CLARITY.
05399-027
Figure 34. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the V
IN
+ and V
IN
− pins in
each differential pair (V
IN
+ − V
IN
−). V
IN
+ and V
IN
− should
be simultaneously driven by two signals each of amplitude
±4 × VREF (depending on the input range selected) that
are 180° out of phase. Assuming the ±4 × VREF mode, the
amplitude of the differential signal is −20 V to +20 V p-p
(2 × 4 × VREF), regardless of the common mode.
The common mode is the average of the two signals
(V
IN
+ + V
IN
−)/2
and is, therefore, the voltage on which the two input signals are
centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common-mode range is
determined by the output swing of the amplifier. If the
differential inputs are not driven from an amplifier, the
common-mode range is determined by the supply voltage on
the V
DD
supply pin and the V
SS
supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × VREF) to
+2 × (4 × VREF) corresponding to digital codes −4096 to +4095.